 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| www.renesas.com all information contained in these materials, including products and product specifications, represents information on the product at the ti me of publication and is subject to change by renesas technology corp. without notice. please review the latest information published by renesas technology corp. through various means, including the renesas technology corp. website (http://www.renesas.com). rej09b0385-0100 16/32 m32c/8a group hardware manual renesas mcu m16c family / m32c/80 series rev.1.00 revision date:jul 15, 2007
1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. how to use this manual 1. purpose and target readers this manual is designed to provide the user with an understanding of the hardwa re functions and electrical characteristics of the mcu. it is intended for users de signing application systems incorporating the mcu. a basic knowledge of electric circuits, logi cal circuits, and mcus is necessa ry in order to use this manual. the manual comprises an overview of the product; descriptions of the cpu, system control functions, peripheral functions, and electrical charac teristics; and usage notes. particular attention should be paid to the precautio nary notes when using the manual. these notes occur within the body of the text, at the end of each section, and in the usage notes section. the revision history summarizes the loca tions of revisions and additions. it does not list all revisions. refer to the text of the manual for details. the following documents apply to the m32c/8a group. make su re to refer to the latest versions of these documents. the newest versions of the documents listed may be obtained from the renesas technology web site. document type description document title document no. datasheet hardware overview and electr ical characteristics m32c/8a group datasheet rej03b0213- 0110 hardware manual hardware specifications (pin assignments, memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description note: refer to the applic ation notes for details on using peripheral functions. m32c/8a group hardware manual this hardware manual software manual description of cpu instruction set m32c/80 series software manual rej09b0319- 0100 application note information on using peripheral functions and application examples sample programs information on writing programs in assembly language and c available from renesas technology web site. renesas technical update product specifications, updates on documents, etc. 2. notation of numbers and symbols the notation conventions for register na mes, bit names, numbers, and symbols used in this manual are described below. (1) register names, bit names, and pin names registers, bits, and pins are referred to in the text by symbols. the symbol is accompanied by the word ?register,? ?bit,? or ?pin? to distinguish the three categories. examples the pm03 bit in the pm0 register p3_5 pin, vcc pin (2) notation of numbers the indication ?b? is appended to numeric values given in binary format. however, nothing is appended to the values of single bits. the indication ?h? is appended to numeric values given in hexadecimal format. nothing is appended to numeric values given in decimal format. examples binary: 11b hexadecimal: efa0h decimal: 1234 3. register notation the symbols and terms used in register diagrams are described below. *1 blank: set to 0 or 1 acco rding to the application. 0: set to 0. 1: set to 1. x: unimplemented. *2 rw: read and write. ro: read only. wo: write only. ? : unimplemented. *3 ? reserved bit reserved bit. set to specified value. *4 ? unimplemented nothing is implemented to the bit. as the bit may be used for future functions, if necessary, set to 0. ? do not set to a value operation is not guaranteed when a value is set. ? function varies according to the operating mode. the function of the bit varies with the peripheral functi on mode. refer to the regist er diagram for information on the individual modes. xxx register symbol address after reset xxx xxx 00h bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 xxx bits 1 0: xxx 0 1: xxx 1 0: do not set to this value 1 1: xxx b1 b0 xxx1 xxx0 xxx4 reserved bit xxx5 xxx7 xxx6 function unimplemented. write 0. read as undefined value. xxx bit function varies depending on each operation mode set to 0 0 (b3) (b2) rw rw rw rw wo rw ro xxx bits 0: xxx 1: xxx *1 *2 *3 *4 4. list of abbrevia tions and acronyms abbreviation full form acia asynchronous communication interface adapter bps bits per second crc cyclic redundancy check dma direct memory access dmac direct memory access controller gsm global system for mobile communications hi-z high impedance iebus inter equipment bus i/o input/output irda infrared data association lsb least significant bit msb most significant bit nc non-connection pll phase locked loop pwm pulse width modulation sfr special function registers sim subscriber identity module uart universal asynchrono us receiver/transmitter vco voltage controlled oscillator all trademarks and registered trademarks are the property of their respective owners. iebus is a registered trademark of nec electronics corporation. a - 1 special function register (sfr) page reference ............................................................................ b- 1 1. overview .................................................................................................................... ..................... 1 1.1 features ................................................................................................................... .................................. 1 1.1.1 applications ............................................................................................................. ............................. 1 1.1.2 specifications ........................................................................................................... ............................. 1 1.2 product list ............................................................................................................... ................................ 6 1.3 block diagram .............................................................................................................. ............................ 7 1.4 pin assignments ............................................................................................................ ............................ 8 1.5 pin functions .............................................................................................................. ............................. 15 2. central processing unit (cpu) ....................... ........................................................................ ...... 18 2.1 general registers .......................................................................................................... .......................... 19 2.1.1 data registers (r0, r1, r2, and r3) ...................................................................................... ............ 19 2.1.2 address registers (a0 and a1) ............................................................................................ .............. 19 2.1.3 static base register (sb) ................................................................................................ ................... 19 2.1.4 frame base register (fb) ................................................................................................. ................. 19 2.1.5 user stack pointer (usp) and inte rrupt stack pointer (isp) .............................................................. 19 2.1.6 interrupt table register (intb) ................. ......................................................................... ............... 19 2.1.7 program counter (pc) ..................................................................................................... ................... 19 2.1.8 flag register (flg) ................................. ..................................................................... ...................... 19 2.2 high-speed interrupt registers ....................... ...................................................................... .................. 20 2.3 dmac-associated registers ............................. ..................................................................... ................ 20 3. memory ...................................................................................................................... ................... 21 4. special function registers (sfrs) ........................................................................................... .... 22 5. reset ....................................................................................................................... ...................... 33 5.1 hardware reset 1 ........................................................................................................... ......................... 33 5.1.1 reset at a stable supply voltage ......................................................................................... ............... 33 5.1.2 power-on reset ........................................................................................................... ........................ 33 5.2 hardware reset 2 (vdet3 detection function) ....... ......................................................................... ......... 35 5.3 software reset ............................................................................................................. ........................... 35 5.4 watchdog timer reset ....................................................................................................... ..................... 35 5.5 internal registers ......................................................................................................... ........................... 36 6. power supply voltage detection function .................................................................................... 37 6.1 vdet3 detection function ................................................................................................... .................... 41 6.2 vdet4 detection function ................................................................................................... .................... 42 6.2.1 usage notes on vdet4 detection interrupt ................................................................................. ........ 44 6.3 cold start/warm start de termine function ................................................................................... ......... 44 7. processor mode .............................................................................................................. .............. 45 7.1 processor mode ............................................................................................................. .......................... 45 7.2 setting of processor mode .................................................................................................. .................... 45 8. bus ......................................................................................................................... ....................... 49 8.1 bus settings ............................................................................................................... .............................. 49 table of contents a - 2 8.1.1 selecting external address bus ....................... .................................................................... .............. 50 8.1.2 selecting external data bus .............................................................................................. ................. 50 8.1.3 selecting separate/multiplexed bus ....................................................................................... ............ 50 8.2 bus control ................................................................................................................ ............................. 52 8.2.1 address bus and data bus ................................................................................................. ................ 52 8.2.2 chip-select output ....................................................................................................... ...................... 52 8.2.3 read/write output signals ................................................................................................ ................. 54 8.2.4 bus timing ............................................................................................................... .......................... 55 8.2.5 ale output ............................................................................................................... ......................... 63 8.2.6 rdy input ........... ........... ........... ........... ............ ........... ........... ........... ........... ........... ......... .................................... 63 8.2.7 hold input ........................................................................................................................ ................ 64 8.2.8 external bus states when acce ssing internal space ...... .............. .............. .............. .............. .......... .. 65 8.2.9 bclk output .............................................................................................................. ....................... 65 8.3 page mode control function ................................................................................................. ................. 66 9. clock generation circuits ............................... .................................................................... .......... 69 9.1 types of the clock generation circuit ...................................................................................... ............. 69 9.1.1 main clock ............................................................................................................... .......................... 78 9.1.2 sub clock ................................................................................................................ ........................... 79 9.1.3 on-chip oscillator clock .. ............................................................................................... .................. 80 9.1.4 pll clock ................................................................................................................ ........................... 81 9.2 cpu clock and bclk ......................................................................................................... ................... 83 9.3 peripheral function clock .................................................................................................. ..................... 83 9.3.1 f1, f8, f32, and f2n ..................................................................................................... ......................... 83 9.3.2 fad ...................................................................................................................... ............................... 83 9.3.3 fc32 ..................................................................................................................... ............................... 83 9.4 clock output function ...................................................................................................... ...................... 84 9.5 power consumption control .................................................................................................. ................. 85 9.5.1 cpu operating mode ....................................................................................................... ................... 85 9.5.2 wait mode ................................................................................................................ .......................... 87 9.5.3 stop mode ................................................................................................................ ........................... 90 9.6 system clock protect function .............................................................................................. ................. 93 10. protection ................................................................................................................. ..................... 94 11. interrupts ................................................................................................................. ...................... 95 11.1 types of interrupts ....................................................................................................... ........................... 95 11.2 software interrupts ....................................................................................................... ........................... 96 11.2.1 undefined instruction interrupt ......................................................................................... ................. 96 11.2.2 overflow interrupt ...................................................................................................... ........................ 96 11.2.3 brk interrupt ........................................................................................................... .......................... 96 11.2.4 brk2 interrupt .......................................................................................................... ......................... 96 11.2.5 int instruction interrupt ............................................................................................... ..................... 96 11.3 hardware interrupts ....................................................................................................... ......................... 97 11.3.1 special interrupts ...................................................................................................... .......................... 97 11.3.2 dmacii transfer complete interrupt ...................................................................................... ......... 97 11.3.3 peripheral function interrupt ........................................................................................... ................... 97 11.4 high-speed interrupt ...................................................................................................... ......................... 98 11.5 interrupts and interrupt vectors .......................................................................................... .................... 99 11.5.1 fixed vector table ...................................................................................................... ....................... 99 a - 3 11.5.2 relocatable vector table ................................................................................................ ................... 99 11.6 interrupt request acknowledgement ......................................................................................... ........... 102 11.6.1 i flag and ipl .......................................................................................................... ......................... 102 11.6.2 interrupt control registers and rlvl register ........................................................................... .... 102 11.6.3 interrupt sequence ...................................................................................................... ...................... 106 11.6.4 interrupt response time ................................................................................................. ................. 107 11.6.5 ipl change when interrupt request is acknowledged .................................................................... 10 8 11.6.6 saving a register ....................................................................................................... ....................... 108 11.6.7 returning from interrupt rout ine ........................................................................................ ............. 109 11.6.8 interrupt priority ...................................................................................................... ......................... 109 11.6.9 interrupt priority level select circuit ................................................................................. ............. 109 11.7 int interrupt .................................................................................................................... ..................... 111 11.8 nmi interrupt .................................................................................................................... .................... 114 11.9 key input interrupt ....................................................................................................... ......................... 114 11.10 address match interrupt .................................................................................................. ..................... 115 12. watchdog timer ............................................................................................................. ............. 116 13. dmac ....................................................................................................................... .................. 120 13.1 transfer cycles ........................................................................................................... .......................... 130 13.1.1 effect of source and destination addresses .............................................................................. ...... 130 13.1.2 effect of the ds register ............................................................................................... ................... 130 13.1.3 effect of software wait state ........................................................................................... ................ 130 13.1.4 effect of the rdy signal .................................................................................................................. 130 13.2 dma transfer time ......................................................................................................... .................... 131 13.3 channel priority and dma transf er timing .................................................................................. ...... 131 14. dmacii ..................................................................................................................... .................. 133 14.1 dmacii settings ........................................................................................................... ....................... 133 14.1.1 rlvl register ........................................................................................................... ...................... 133 14.1.2 dmacii index ............................................................................................................ ..................... 135 14.1.3 interrupt control register for the peripheral fu nction .................................................................. .. 137 14.1.4 relocatable vector table for the peripheral func tion .................................................................... . 137 14.2 dmacii performance ........................................................................................................ ................... 137 14.3 transfer data ............................................................................................................. ............................ 137 14.3.1 memory-to-memory transfer ............................................................................................... ............ 137 14.3.2 immediate data transfer ................................................................................................. ................. 138 14.3.3 calculation transfer .................................................................................................... ..................... 138 14.4 transfer modes ............................................................................................................ ......................... 138 14.4.1 single transfer ......................................................................................................... ........................ 138 14.4.2 burst transfer .......................................................................................................... ......................... 138 14.4.3 multiple transfer ....................................................................................................... ....................... 138 14.5 chain transfer ............................................................................................................ ........................... 139 14.6 end-of-transfer interrupt ................................................................................................. ..................... 139 14.7 execution time ............................................................................................................ ......................... 140 15. timers ..................................................................................................................... .................... 141 15.1 timer a ................................................................................................................... .............................. 143 15.1.1 timer mode .............................................................................................................. ........................ 155 a - 4 15.1.2 event counter mode ...................................................................................................... ................... 156 15.1.3 one-shot timer mode ..................................................................................................... ................. 161 15.1.4 pulse width modulation mode ............................................................................................. ............ 163 15.2 timer b ................................................................................................................... .............................. 166 15.2.1 timer mode .............................................................................................................. ........................ 173 15.2.2 event counter mode ...................................................................................................... ................... 174 15.2.3 pulse period measurement mode, pulse width m easurement mode .............................................. 175 16. three-phase motor control timer function ............................................................................... 178 16.1 triangular wave modulation mode ........................................................................................... ........... 189 16.2 sawtooth wave modulation mode .............. .............. .............. ............... .............. ........... ........... .......... 193 16.3 short circuit prevention featur es ......................................................................................... ................ 195 16.3.1 prevention against upper/lower arm short circui t by program errors ........................................ 195 16.3.2 arm short circuit prevention using dead time time r ................................................................... 19 5 16.3.3 forced-cutoff function by the nmi input ....................................................................................... 195 17. serial interfaces .......................................................................................................... ................ 196 17.1 uart0 to uart4 ............................................................................................................ .................... 197 17.1.1 clock synchronous mode .................................................................................................. .............. 207 17.1.2 clock asynchronous (uart) mode ............. .............. .............. .............. .............. ............ ......... ...... 216 17.1.3 special mode 1 (i2c mode) ............................................................................................... .............. 224 17.1.4 special mode 2 .......................................................................................................... ....................... 236 17.1.5 special mode 3 (gci mode) ............................................................................................... ............. 241 17.1.6 special mode 4 (sim mode) ............................................................................................... ............. 245 18. a/d converter .............................................................................................................. ............... 251 18.1 mode descriptions ......................................................................................................... ....................... 259 18.1.1 one-shot mode ........................................................................................................... ...................... 260 18.1.2 repeat mode ............................................................................................................. ........................ 261 18.1.3 single sweep mode ....................................................................................................... ................... 262 18.1.4 repeat sweep mode 0 ..................................................................................................... ................. 263 18.1.5 repeat sweep mode 1 ..................................................................................................... ................. 264 18.1.6 multi-port single sweep mode ............................................................................................ ............ 266 18.1.7 multi-port repeat sweep mode 0 .......................................................................................... .......... 267 18.2 functions ................................................................................................................. .............................. 268 18.2.1 resolution .............................................................................................................. ........................... 268 18.2.2 sample and hold ......................................................................................................... ..................... 268 18.2.3 trigger select function ................................................................................................. ................... 268 18.2.4 dmac operating mode ..................................................................................................... .............. 268 18.2.5 extended analog input pins .............................................................................................. ............... 268 18.2.6 external operating amplifier (op-amp) connection mode ........................................................... 269 18.2.7 power consumption reduce function ....................................................................................... ...... 269 18.3 read from the ad0i register (i = 0 to 7) ..... ............................................................................. ............ 270 18.4 output impedance of sensor equivalent circuit under a/d conversion ............... ............ ........... ....... 270 a - 5 19. d/a converter .............................................................................................................. ............... 272 20. crc calculation ............................................................................................................ ............. 274 21. x/y conversion ............................................................................................................. .............. 276 22. programmable i/o ports ..................................................................................................... ........ 279 22.1 port pi direction register (pdi register, i = 0 to 15) .................................................................... ....... 279 22.2 port pi register (pi register, i = 0 to 15) .. ............................................................................. ............... 279 22.3 function select register a (psj register, j = 0 to 3) ..................................................................... ....... 279 22.4 function select register b (pslk register, k = 0 to 3) .................................................................... .... 279 22.5 function select register c (psc register) ................................................................................. .......... 279 22.6 pull-up control register 0 to 4 (pur0 to pur4 regi sters) ................................................................. 280 22.7 port control register (pcr re gister) ...................................................................................... ............. 280 22.8 analog input and other peripheral function input .......................................................................... ..... 280 23. electrical characteristics ....................... .......................................................................... ............ 299 24. usage notes ............................................................................................................... ............... 331 24.1 power supply .............................................................................................................. .......................... 331 24.1.1 power-on ................................................................................................................ ........................... 331 24.1.2 power supply ripple ..................................................................................................... ................... 332 24.1.3 noise ................................................................................................................... .............................. 332 24.2 special function registers (sfr s) ......................................................................................... ............... 333 24.2.1 100 pin-package ......................................................................................................... ...................... 333 24.2.2 register settings ....................................................................................................... ........................ 333 24.3 clock generation circuits ................................................................................................. .................... 334 24.3.1 main clock .............................................................................................................. ......................... 334 24.3.2 sub clock ............................................................................................................... .......................... 334 24.3.3 clock dividing ratio .................................................................................................... .................... 334 24.3.4 power consumption control ............................................................................................... ............. 334 24.4 protection ................................................................................................................ .............................. 337 24.5 interrupts ................................................................................................................ ............................... 338 24.5.1 isp setting ............................................................................................................. ........................... 338 24.5.2 nmi interrupt .................................................................................................................... ............... 338 24.5.3 int interrupt .................................................................................................................... ................. 338 24.5.4 changing interrupt control register ..................................................................................... ........... 340 24.5.5 changing rlvl register .................................................................................................. ............... 340 24.6 dmac ...................................................................................................................... ............................. 341 24.7 timers .................................................................................................................... ............................... 342 24.7.1 timer a, timer b ........................................................................................................ ..................... 342 24.7.2 timer a ................................................................................................................. ............................ 342 24.7.3 timer b ................................................................................................................. ............................ 344 24.8 three-phase motor control timer function ......... ......................................................................... ....... 345 24.9 serial interfaces ..... .............. .............. .............. .............. ........... ............ ........... .......... ............................ 346 24.9.1 changing uibrg register (i = 0 to 4) .................................................................................... ......... 346 24.9.2 clock synchronous mode .................................................................................................. .............. 346 24.9.3 uart mode ............................................................................................................... ...................... 346 24.9.4 special mode 1 (i2c mode) ............................................................................................... .............. 346 24.10 a/d converter ............................................................................................................ ........................... 347 a - 6 24.11 programmable i/o ports ................................................................................................... ..................... 349 appendix 1. package dimensions ............................................................................................... .. 350 index ........................................................................................................................ ............................. 351 b - 1 blank spaces are reserved. no access is allowed. blank spaces are reserved. no access is allowed. address register symbol page 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 46 0005h processor mode register 1 pm1 47 0006h system clock control register 0 cm0 71, 118 0007h system clock control register 1 cm1 72 0008h 0009h address match interrupt enable register aier 115 000ah protect register prcr 94 000bh external data bus width control register ds 49 000ch main clock division register mcd 73 000dh oscillation stop detection register cm2 74 000eh watchdog timer start register wdts 40, 119 000fh watchdog timer control register wdc 119 0010h address match interrupt register 0 rmad0 115 0011h 0012h 0013h processor mode register 2 pm2 76 0014h address match interrupt register 1 rmad1 115 0015h 0016h 0017h voltage detection register 2 vcr2 38 0018h address match interrupt register 2 rmad2 115 0019h 001ah 001bh voltage detection register 1 vcr1 38 001ch address match interrupt register 3 rmad3 115 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h pll control register 0 plc0 75 0027h pll control register 1 plc1 75 0028h address match interrupt register 4 rmad4 115 0029h 002ah 002bh 002ch address match interrupt register 5 ramd5 115 002dh 002eh 002fh vdet4 detection interrupt register d4int 39 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h address match interrupt register 6 rmad6 115 0039h 003ah 003bh 003ch address match interrupt register 7 rmad7 115 003dh 003eh 003fh address register symbol page 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h external space wait control register 0 ewcr0 55 0049h external space wait control register 1 ewcr1 55 004ah external space wait control register 2 ewcr2 55 004bh external space wait control register 3 ewcr3 55 004ch page mode wait control register 0 pwcr0 66 004dh page mode wait control register 1 pwcr1 67 004eh 004fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h dma0 control register dm0ic 103 0069h timer b5 interrupt control register tb5ic 006ah dma2 control register dm2ic 006bh uart2 receive/ack interrupt control register s2ric 006ch timer a0 interrupt control register ta0ic 006dh uart3 receive/ack interrupt control register s3ric 006eh timer a2 interrupt control register ta2ic 006fh uart4 receive/ack interrupt control register s4ric 0070h timer a4 interrupt control register ta4ic 0071h uart0/uart3 bus conflict detection interrupt control register bcn0ic/ bcn3ic 0072h uart0 receive/ack interrupt control register s0ric 0073h a/d0 conversion interrput control register ad0ic 0074h uart1 receive/ack interrupt control register s1ric 0075h i 0076h timer b1 interrupt control register tb1ic 103 0077h 0078h timer b3 interrupt control register tb3ic 103 0079h 007ah int5 interrupt control register int5ic 104 007bh 007ch int3 interrupt control register int3ic 104 007dh 007eh int1 interrupt control register int1ic 104 007fh special function register (sfr) page reference b - 2 blank spaces are reserved. no access is allowed. blank spaces are reserved. no access is allowed. address register symbol page 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h dma1 interrupt control register dm1ic 103 0089h uart2 transmit/nack interrupt control register s2tic 008ah dma3 interrupt control register dm3ic 008bh uart3 transmit/nack interrupt control register s3tic 008ch timer a1 interrupt control register ta1ic 008dh uart4 transmit/nack interrupt control register s4tic 008eh timer a3 interrupt control register ta3ic 008fh uart2 bus conflict detection interrupt control register bcn2ic 0090h uart0 transmit/nack interrupt control register s0tic 0091h uart1/uart4 bus conflict detection interrupt control register bcn1ic/ bcn4ic 0092h uart1 transmit complete interrupt control register s1tic 0093h key input interrupt control register kupic 0094h timer b0 interrupt control register tb0ic 0095h 0096h timer b2 interrupt control register tb2ic 103 0097h ii/o interrupt control register 3/ can2 interrupt control register 1 iio3ic/ can21ic 0098h timer b4 interrupt control register tb4ic 103 0099h 009ah int4 interrupt control register int4ic 104 009bh 009ch int2 interrupt control register int2ic 104 009dh 103 009eh int0 interrupt control register int0ic 104 009fh exit priority register rlvl 105, 134 00a0h 00a1h 00a2h 00a3h 00a4h 00a5h 00a6h 00a7h 00a8h 00a9h 00aah 00abh 00ach 00adh 00aeh 00afh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh 00bch 00bdh 00beh 00bfh to 02bfh address register symbol page 02c0h x0 register, y0 register x0r, y0r 276 02c1h 02c2h x1 register, y1 register x1r , y1r 02c3h 02c4h x2 register, y2 register x2r , y2r 02c5h 02c6h x3 register, y3 register x3r , y3r 02c7h 02c8h x4 register, y4 register x4r , y4r 02c9h 02cah x5 register, y5 register x5r , y5r 02cbh 02cch x6 register, y6 register x6r , y6r 02cdh 02ceh x7 register, y7 register x7r , y7r 02cfh 02d0h x8 register, y8 register x8r , y8r 02d1h 02d2h x9 register, y9 register x9r , y9r 02d3h 02d4h x10 register, y10 register x10r , y10r 02d5h 02d6h x11 register, y11 register x11r , y11r 02d7h 02d8h x12 register, y12 register x12r , y12r 02d9h 02dah x13 register, y13 register x13r , y13r 02dbh 02dch x14 register, y14 register x14r , y14r 02ddh 02deh x15 register, y15 register x15r , y15r 02dfh 02e0h x/y control register xyc 276 02e1h 02e2h 02e3h 02e4h uart1 special mode register 4 u1smr4 202 02e5h uart1 special mode register 3 u1smr3 201 02e6h uart1 special mode register 2 u1smr2 200 02e7h uart1 special mode register u1smr 199 02e8h uart1 transmit/receive mode register u1mr 198 02e9h uart1 baud rate register u1brg 204 02eah uart1 transmit buffer register u1tb 206 02ebh 02ech uart1 transmit/receive control register 0 u1c0 203 02edh uart1 transmit/receive control register 1 u1c1 204 02eeh uart1 receive buffer register u1rb 206 02efh 02f0h 02f1h 02f2h 02f3h 02f4h uart4 special mode register 4 u4smr4 202 02f5h uart4 special mode register 3 u4smr3 201 02f6h uart4 special mode register 2 u4smr2 200 02f7h uart4 special mode register u4smr 199 02f8h uart4 transmit/receive mode register u4mr 198 02f9h uart4 baud rate register u4brg 204 02fah uart4 transmit buffer register u4tb 206 02fbh 02fch uart4 transmit/receive control register 0 u4c0 203 02fdh uart4 transmit/receive control register 1 u4c1 204 02feh uart4 receive buffer register u4rb 206 02ffh 0300h timer b3, b4, b5 count start flag tbsr 171 0301h 0302h timer a11 register ta11 187 0303h 0304h timer a21 register ta21 0305h 0306h timer a41 register ta41 0307h 0308h three-phase pwm control register 0 invc0 180 0309h three-phase pwm control register 1 invc1 181 030ah three-phase output buffer register 0 idb0 187 030bh three-phase output buffer register 1 idb1 187 030ch dead time timer dtt 186 030dh timer b2 interrupt generation frequency set counter ictb2 185 030eh 030fh special function register (sfr) page reference b - 3 blank spaces are reserved. no access is allowed. blank spaces are reserved. no access is allowed. address register symbol page 0310h timer b3 register tb3 170 0311h 0312h timer b4 register tb4 0313h 0314h timer b5 register tb5 0315h 0316h 0317h 0318h 0319h 031ah 031bh timer b3 mode register tb3mr 167, 168, 169 031ch timer b4 mode register tb4mr 031dh timer b5 mode register tb5mr 031eh 031fh external interrupt source select register ifsr 113, 205 0320h 0321h 0322h 0323h 0324h uart3 special mode register 4 u3smr4 202 0325h uart3 special mode register 3 u3smr3 201 0326h uart3 special mode register 2 u3smr2 200 0327h uart3 special mode register u3smr 199 0328h uart3 transmit/receive mode register u3mr 198 0329h uart3 baud rate register u3brg 204 032ah uart3 transmit buffer register u3tb 206 032bh 032ch uart3 transmit/receive control register 0 u3c0 203 032dh uart3 transmit/receive control register 1 u3c1 204 032eh uart3 receive buffer register u3rb 206 032fh 0330h 0331h 0332h 0333h 0334h uart2 special mode register 4 u2smr4 202 0335h uart2 special mode register 3 u2smr3 201 0336h uart2 special mode register 2 u2smr2 200 0337h uart2 special mode register u2smr 199 0338h uart2 transmit/receive mode register u2mr 198 0339h uart2 baud rate register u2brg 204 033ah uart2 transmit buffer register u2tb 206 033bh 033ch uart2 transmit/receive control register 0 u2c0 203 033dh uart2 transmit/receive control register 1 u2c1 204 033eh uart2 receive buffer register u2rb 206 033fh 0340h count start register tabsr 152, 171, 188 0341h clock prescaler reset registe cpsrf 77 0342h one-shot start register onsf 153 0343h trigger select register trgsr 151, 184 0344h up/down flag udf 150 0345h 0346h timer a0 register ta0 149 0347h 0348h timer a1 register ta1 0349h 034ah timer a2 register ta2 034bh 044ch timer a3 register ta3 034dh 034eh timer a4 register ta4 034fh 0350h timer b0 register tb0 170 0351h 0352h timer b1 register tb1 0353h 0354h timer b2 register tb2 0355h 0356h timer a0 mode register ta0mr 145, 146, 147, 148 0357h timer a1 mode register ta1mr 0358h timer a2 mode register ta2mr 0359h timer a3 mode register ta3mr 035ah timer a4 mode register ta4mr 035bh timer b0 mode register tb0mr 167, 168, 169 035ch timer b1 mode register tb1mr 035dh timer b2 mode register tb2mr 035eh timer b2 special mode register tb2sc 185 035fh count source prescaler register tcspr 77, 144 address register symbol page 0360h 0361h 0362h 0363h 0364h uart0 special mode register 4 u0smr4 202 0365h uart0 special mode register 3 u0smr3 201 0366h uart0 special mode register 2 u0smr2 200 0367h uart0 special mode register u0smr 199 0368h uart0 transmit/receive mode register u0mr 198 0369h uart0 baud rate register u0brg 204 036ah uart0 transmit buffer register u0tb 206 036bh 036ch uart0 transmit/receive control register 0 u0c0 203 036dh uart0 transmit/receive control register 1 u0c1 204 036eh uart0 receive buffer register u0rb 206 036fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h dma0 request source select register dm0sl 122 0379h dma1 request source select register dm1sl 037ah dma2 request source select register dm2sl 037bh dma3 request source select register dm3sl 037ch crc data register crcd 274 037dh 037eh crc input register crcin 274 037fh 0380h a/d0 register 0 ad00 258 0381h 0382h a/d0 register 1 ad01 0383h 0384h a/d0 register 2 ad02 0385h 0386h a/d0 register 3 ad03 0387h 0388h a/d0 register 4 ad04 0389h 038ah a/d0 register 5 ad05 038bh 038ch a/d0 register 6 ad06 038dh 038eh a/d0 register 7 ad07 038fh 0390h 0391h 0392h a/d0 control register 4 ad0con4 258 0393h 0394h a/d0 control register 2 ad0con2 256 0395h a/d0 control register 3 ad0con3 257 0396h a/d0 control register 0 ad0con0 254 0397h a/d0 control register 1 ad0con1 255 0398h d/a register 0 da0 273 0399h 039ah d/a register 1 da1 273 039bh 039ch d/a control register dacon 273 039dh 039eh 039fh 03a0h 03a1h 03a2h 03a3h 03a4h 03a5h 03a6h 03a7h 03a8h 03a9h 03aah 03abh 03ach 03adh 03aeh 03afh function select register c psc 290 special function register (sfr) page reference b - 4 blank spaces are reserved. no access is allowed. address register symbol page 03b0h function select register a0 ps0 286 03b1h function select register a1 ps1 286 03b2h function select register b0 psl0 288 03b3h function select register b1 psl1 288 03b4h function select register a2 ps2 287 03b5h function select register a3 ps3 287 03b6h function select register b2 psl2 289 03b7h function select register b3 psl3 289 03b8h 03b9h 03bah 03bbh 03bch 03bdh 03beh 03bfh 03c0h port p6 register p6 285 03c1h port p7 register p7 285 03c2h port p6 direction register pd6 284 03c3h port p7 direction register pd7 284 03c4h port p8 register p8 285 03c5h port p9 register p9 285 03c6h port p8 direction register pd8 284 03c7h port p9 direction register pd9 284 03c8h port p10 register p10 285 03c9h port p11 register p11 285 03cah port p10 direction register pd10 284 03cbh port p11 direction register pd11 284 03cch port p12 register p12 285 03cdh port p13 register p13 285 03ceh port p12 direction register pd12 284 03cfh port p13 direction register pd13 284 03d0h port p14 register p14 285 03d1h port p15 register p15 285 03d2h port p14 direction register pd14 284 03d3h port p15 direction register pd15 284 03d4h 03d5h 03d6h 03d7h 03d8h 03d9h 03dah pull-up control register 2 pur2 292 03dbh pull-up control register 3 pur3 293 03dch pull-up control register 4 pur4 294 03ddh 03deh 03dfh 03e0h port p0 register p0 285 03e1h port p1 register p1 285 03e2h port p0 direction register pd0 284 03e3h port p1 direction register pd1 284 03e4h port p2 register p2 285 03e5h port p3 register p3 285 03e6h port p2 direction register pd2 284 03e7h port p3 direction register pd3 284 03e8h port p4 register p4 285 03e9h port p5 register p5 285 03eah port p4 direction register pd4 284 03ebh port p5 direction register pd5 284 03ech 03edh 03eeh 03efh 03f0h pull-up control register 0 pur0 291 03f1h pull-up control register 1 pur1 291 03f2h 03f3h 03f4h 03f5h 03f6h 03f7h 03f8h 03f9h 03fah 03fbh 03fch 03fdh 03feh 03ffh port control register pcr 295 special function register (sfr) page reference rev.1.00 jul 15, 2007 page 1 of 352 rej09b0385-0100 m32c/8a group renesas mcu 1. overview 1.1 features the m32c/8a group is a single-chip control mcu, fa bricated using high-performance silicon gate cmos technology, embedding the m32c/80 series cpu core. the m32c/8a group is housed in 144-pin and 100-pin plastic molded lqfp packages. with a 16-mbyte address space, this mcu combines adva nced instruction manipulatio n capabilities to process complex instructions by less bytes and execute instructions at higher speed. the m32c/8a group has a multiplier and dmac adequa te for office automation, communication devices and industrial equipment, and other high-speed processing applications. 1.1.1 applications audio, cameras, office/communica tion/portable eq uipment, etc. 1.1.2 specifications tables 1.11.3 to 1.4 lists the specifications of the m32c/8a group. the m32c/8a group is romless device. use the m32c/8a group in microprocessor mode after reset. m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 2 of 352 rej09b0385-0100 table 1.1 specifications (144-pin version) (1) item function specification cpu central processing unit m32c/80 core (multiplier: 16 bits 16 bits 32 bits, multiply-addition operation instructions: 16 16 + 48 48 bits) ? basic instructions: 108 ? minimum instruction execution time: 31.3 ns ( f(cpu) = 32 mhz / vcc1 = 4.2 to 5.5 v) 41.7 ns ( f(cpu) = 24 mhz / vcc1 = 3.0 to 5.5 v) ? operating mode: microprocessor mode memory rom, ram see table 1.5 product list . power supply voltage detection vdet3 detection functi on, vdet4 detection function, cold start/warm start determination function external bus expansion bus / memory expansion function ? address space: 16 mbyte ? external bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 v and 5 v interfaces ? bus format: switchable between separate and multiplexed bus formats, switchable data bu s width (8-bit or 16-bit) clock clock generation circuits ? 4 circuits: main clock, sub clock, on-chip oscillator, pll frequency synthesizer ? oscillation stop detection: main clock oscillation stop detectio n function ? frequency divider circuit: dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 ? low power consumption features: wait mode, stop mode interrupts ? interrupt vectors: 70 ? external interrupt inputs: nmi 1 int 3 (16-bit external bus width) int 6 (8- bit external bus width) key input 4 ? interrupt priority levels: 7 watchdog timer 15-bit 1 (with prescaler) dma dmac ? 4 channels, cycle steal method ? trigger sources: 31 ? transfer modes: 2 (single transfer and repeat transfer) dmac ii ? can be activated by all peripheral function interrupt sources ? transfer modes: 2 (single transfer and burst transfer) ? immediate transfer, calculation transfer, and chain transfer functions timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse width modulation (pwm) mode) event counter 2-phase pulse signal processing (2-phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode timer function for 3-phase motor control 3-phase inverter control 1 (using timer a1, timer a2, timer a4, and timer b2) on-chip dead time timer m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 3 of 352 rej09b0385-0100 table 1.2 specifications (144-pin version) (2) notes: 1. iebus is a registered trademark of nec electronics corporation. 2. please contact a renesas sales office to use the optional feature. item function specification serial interface uart0 to uart4 clock synchr onous / asynchronous 5 i 2 c bus (optional) (2) , special mode 2, gci mode, sim mode iebus (optional) (1)(2) a/d converter 10-bit resolution x 18 channels, includes sample and hold function d/a converter 8-bit re solution 2 channels crc calculation circuit crc-ccitt (x 16 + x 12 + x 5 + 1) compliant x/y converter 16 bits x 16 bits i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 81 (8-bit external bus width) 73 (16-bit external bus width) with selectable pull-up resistor ? n channel open drain ports: 2 operating frequency / supply voltage 32 mhz: vcc1 = 4.2 to 5.5 v, vcc2 = 3.0 to vcc1 24 mhz: vcc1 = 3.0 to 5.5 v, vcc2 = 3.0 to vcc1 current consumption 28 ma (32 mhz / vcc1 = vcc2 = 5 v) 22 ma (24 mhz / vcc1 = vcc2 = 3.3 v) 45 a (approx. 1 mhz / vcc1 = vcc2 = 3.3 v, on-chip oscillator low- power consumption mode wait mode) 0.8 a (vcc1 = vcc2 = 3.3 v, stop mode) operating ambient temperature ( c) -20 to 85 c, -40 to 85 c (optional) (2) package 144-pin lqfp (plqp0144ka-a) m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 4 of 352 rej09b0385-0100 table 1.3 specifications (100-pin version) (1) item function specification cpu central processing unit m32c/80 core (multiplier: 16 bits 16 bits 32 bits, multiply-addition operation instructions: 16 16 + 48 48 bits) ? basic instructions: 108 ? minimum instruction execution time: 31.3 ns (f(cpu) = 32 mhz / vcc1 = 4.2 to 5.5 v) 41.7 ns (f(cpu) = 24 mhz / vcc1 = 3.0 to 5.5 v) ? operating mode: microprocessor mode memory rom, ram see table 1.5 product list . power supply voltage detection vdet3 detection functi on, vdet4 detection function, cold start/warm start determination function external bus expansion bus / memory expansion function ? address space: 16 mbyte ? external bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 v and 5 v interfaces ? bus format: switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) clock clock generation circuits ? 4 circuits: main clock, sub clock, on-chip oscillator, pll frequency synthesizer ? oscillation stop detection: main clock oscillation stop detectio n function ? frequency divider circuit: dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 ? low power consumption features: wait mode, stop mode interrupts ? interrupt vectors: 70 ? external interrupt inputs: nmi 1 int 3 (16-bit external bus width) int 6 (8- bit external bus width) key input 4 ? interrupt priority levels: 7 watchdog timer 15-bit 1 (with prescaler) dma dmac ? 4 channels, cycle steal method ? trigger sources: 31 ? transfer modes: 2 (single transfer and repeat transfer) dmacii ? can be activated by all peripheral function interrupt sources ? transfer modes: 2 (single transfer and burst transfer) ? immediate transfer, calculation transfer, and chain transfer functions timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse width modulation (pwm) mode event counter 2-phase pulse signal processing (2-phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode timer function for 3-phase motor control 3-phase inverter control 1 (using timer a1, timer a2, timer a4, and timer b2) on-chip dead time timer m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 5 of 352 rej09b0385-0100 table 1.4 specifications (100-pin version) (2) notes: 1. iebus is a registered trademark of nec electronics corporation. 2. please contact a renesas sales office for optional features. item function specification serial interface uart0 to uart4 clock synchr onous / asynchronous 5 i 2 c bus (optional) (2) , special mode 2, gci mode, sim mode iebus (optional) (1)(2) a/d converter 10-bit resolution x 10 channels, includes sample and hold function d/a converter 8-bit re solution 2 channels crc calculation circuit crc-ccitt (x 16 + x 12 + x 5 + 1) compliant x/y converter 16 bits x 16 bits i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 45 (8-bit external bus width) 37 (16-bit external bus width) with selectable pull-up resistor ? n channel open drain ports: 2 operating frequency / supply voltage 32 mhz: vcc1 = 4.2 to 5.5 v, vcc2 = 3.0 to vcc1 24 mhz: vcc1 = 3.0 to 5.5 v, vcc2 = 3.0 to vcc1 current consumption 28 ma (32 mhz / vcc1 = vcc2 = 5 v) 22 ma (24 mhz / vcc1 = vcc2 = 3.3 v) 45 a (approx. 1 mhz / vcc1 = vcc2 = 3.3 v, on-chip oscillator low- power consumption mode wait mode) 0.8 a (vcc1 = vcc2 = 3.3 v, stop mode) operating ambient temperature ( c) -20 to 85 c, -40 to 85 c (optional) (2) package 100-pin lqfp (plqp0100kb-a) m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 6 of 352 rej09b0385-0100 1.2 product list table 1.5 lists product information. figure 1.1 shows product numbering system. table 1.5 product list (m32c/8a) current as of july. 2007 (p): under planning figure 1.1 product numbering system type no. package rom capacity ram capacity remarks M308A0SGP plqp0100kb-a (100p6q-a) ? 12kb romless m308a3sgp (p) plqp0100kb-a (100p6q-a) 24kb romless m308a5sgp (p) plqp0144ka-a (144p6q-a) 24kb romless part no. m30 8a x s gp package type option gp: package plqp0100kb-a (100p6q-a) package plqp0144ka-a (144p6q-a) memory type s: romless version shows ram capacity, pin count, etc. (the value itself has no specific meaning) m32c/8a group m16c family m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 7 of 352 rej09b0385-0100 1.3 block diagram figure 1.2 shows a m32c/8a group block diagram. figure 1.2 m32c/8a group block diagram port p0 8-bit d/a converters: 2 circuits serial interface: 5 channels clock synchronous/ asynchronous x/y converter: 16 bits 16 bits crc calculation circuit x 16 + x 12 + x 5 + 1 (ccitt) 10-bit a/d converter: 1 circuit, 18 input (3) port p13 port p12 port p11 ram multiplier flg isp intb usp pc svf svp vct m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 8 of 352 rej09b0385-0100 1.4 pin assignments figures 1.3 and 1.4 show a pin assignment (top view). figure 1.3 pin assignment for 144-pin package 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 m32c/8a group plqp0144ka-a (144p6q-a) (top view) m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 9 of 352 rej09b0385-0100 table 1.6 144-pin version list of pin names (1) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 1 p9_6 txd4/sda4/srxd4 anex1 2 p9_5 clk4 anex0 3 p9_4 tb4in cts4 /rts4 /ss4 da1 4 p9_3 tb3in cts3 /rts3 /ss3 da0 5 p9_2 tb2in txd3/sda3/srxd3 6 p9_1 tb1in rxd3/scl3/stxd3 7 p9_0 tb0in clk3 8 p14_6 9 p14_5 10 p14_4 11 p14_3 12 p14_2 13 p14_1 14 p14_0 15 byte 16 cnvss 17 xcin p8_7 18 xcout p8_6 19 reset 20 xout 21 vss 22 xin 23 vcc1 24 p8_5 nmi 25 p8_4 int2 26 p8_3 int1 27 p8_2 int0 28 p8_1 ta4in/u 29 p8_0 ta4out/u 30 p7_7 ta3in 31 p7_6 ta3out 32 p7_5 ta2in/w 33 p7_4 ta2out/w 34 p7_3 ta1in/v cts2 /rts2 /ss2 35 p7_2 ta1out/v clk2 36 p7_1 ta0in/tb5in rxd2/scl2/stxd2 37 p7_0 ta0out txd2/sda2/srxd2 38 p6_7 txd1/sda1/srxd1 39 vcc1 40 p6_6 rxd1/scl1/stxd1 41 vss 42 p6_5 clk1 43 p6_4 cts1 /rts1 /ss1 44 p6_3 txd0/sda0/srxd0 45 p6_2 rxd0/scl0/stxd0 46 p6_1 clk0 47 p6_0 cts0 /rts0 /ss0 48 p13_7 49 p13_6 50 p13_5 m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 10 of 352 rej09b0385-0100 table 1.7 144-pin version list of pin names (2) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 51 p13_4 52 p5_7 rdy 53 p5_6 ale 54 p5_5 hold 55 p5_4 hlda /ale 56 p13_3 57 vss 58 p13_2 59 vcc2 60 p13_1 61 p13_0 62 clkout p5_3 bclk/ale 63 p5_2 rd 64 p5_1 wrh /bhe 65 p5_0 wrl /wr 66 p12_7 67 p12_6 68 p12_5 69 p4_7 cs0 /a23 70 p4_6 cs1 /a22 71 p4_5 cs2 /a21 72 p4_4 cs3 /a20 73 p4_3 a19 74 vcc2 75 p4_2 a18 76 vss 77 p4_1 a17 78 p4_0 a16 79 p3_7 a15,[a15/d15] 80 p3_6 a14,[a14/d14] 81 p3_5 a13,[a13/d13] 82 p3_4 a12,[a12/d12] 83 p3_3 a11,[a11/d11] 84 p3_2 a10,[a10/d10] 85 p3_1 a9,[a9/d9] 86 p12_4 87 p12_3 88 p12_2 89 p12_1 90 p12_0 91 vcc2 92 p3_0 a8,[a8/d8] 93 vss 94 p2_7 a7,[a7/d7] 95 p2_6 a6,[a6/d6] 96 p2_5 a5,[a5/d5] 97 p2_4 a4,[a4/d4] 98 p2_3 a3,[a3/d3] 99 p2_2 a2,[a2/d2] 100 p2_1 a1,[a1/d1] m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 11 of 352 rej09b0385-0100 table 1.8 144-pin version list of pin names (3) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 101 p2_0 a0,[a0/d0] 102 p1_7 int5 d15 103 p1_6 int4 d14 104 p1_5 int3 d13 105 p1_4 d12 106 p1_3 d11 107 p1_2 d10 108 p1_1 d9 109 p1_0 d8 110 p0_7 d7 111 p0_6 d6 112 p0_5 d5 113 p0_4 d4 114 p11_4 115 p11_3 116 p11_2 117 p11_1 118 p11_0 119 p0_3 d3 120 p0_2 d2 121 p0_1 d1 122 p0_0 d0 123 p15_7 an15_7 124 p15_6 an15_6 125 p15_5 an15_5 126 p15_4 an15_4 127 p15_3 an15_3 128 p15_2 an15_2 129 p15_1 an15_1 130 vss 131 p15_0 an15_0 132 vcc1 133 p10_7 ki3 an_7 134 p10_6 ki2 an_6 135 p10_5 ki1 an_5 136 p10_4 ki0 an_4 137 p10_3 an_3 138 p10_2 an_2 139 p10_1 an_1 140 avss 141 p10_0 an_0 142 vref 143 avcc 144 p9_7 rxd4/scl4/stxd4 adtrg m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 12 of 352 rej09b0385-0100 figure 1.4 pin assignment for 100-pin package 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 m32c/8a group plqp0100kb-a (100p6q-a) (top view) m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 13 of 352 rej09b0385-0100 table 1.9 100-pin version list of pin names (1) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 1 p9_4 tb4in cts4 /rts4 /ss4 da1 2 p9_3 tb3in cts3 /rts3 /ss3 da0 3 p9_2 tb2in txd3/sda3/srxd3 4 p9_1 tb1in rxd3/scl3/stxd3 5 p9_0 tb0in clk3 6byte 7 cnvss 8 xcin p8_7 9 xcout p8_6 10 reset 11 xout 12 vss 13 xin 14 vcc1 15 p8_5 nmi 16 p8_4 int2 17 p8_3 int1 18 p8_2 int0 19 p8_1 ta4in/u 20 p8_0 ta4out/u 21 p7_7 ta3in 22 p7_6 ta3out 23 p7_5 ta2in/w 24 p7_4 ta2out/w 25 p7_3 ta1in/v cts2 /rts2 /ss2 26 p7_2 ta1out/v clk2 27 p7_1 ta0in/tb5in rxd2/scl2/stxd2 28 p7_0 ta0out txd2/sda2/srxd2 29 p6_7 txd1/sda1/srxd1 30 p6_6 rxd1/scl1/stxd1 31 p6_5 clk1 32 p6_4 cts1 /rts1 /ss1 33 p6_3 txd0/sda0/srxd0 34 p6_2 rxd0/scl0/stxd0 35 p6_1 clk0 36 p6_0 cts0 /rts0 /ss0 37 p5_7 rdy 38 p5_6 ale 39 p5_5 hold 40 p5_4 hlda /ale 41 clkout p5_3 bclk/ale 42 p5_2 rd 43 p5_1 wrh /bhe 44 p5_0 wrl /wr 45 p4_7 cs0 /a23 46 p4_6 cs1 /a22 47 p4_5 cs2 /a21 48 p4_4 cs3 /a20 49 p4_3 a19 50 p4_2 a18 m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 14 of 352 rej09b0385-0100 table 1.10 100-pin version list of pin names (2) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin 51 p4_1 a17 52 p4_0 a16 53 p3_7 a15,[a15/d15] 54 p3_6 a14,[a14/d14] 55 p3_5 a13,[a13/d13] 56 p3_4 a12,[a12/d12] 57 p3_3 a11,[a11/d11] 58 p3_2 a10,[a10/d10] 59 p3_1 a9,[a9/d9] 60 vcc2 61 p3_0 a8,[a8/d8] 62 vss 63 p2_7 a7,[a7/d7] 64 p2_6 a6,[a6/d6] 65 p2_5 a5,[a5/d5] 66 p2_4 a4,[a4/d4] 67 p2_3 a3,[a3/d3] 68 p2_2 a2,[a2/d2] 69 p2_1 a1,[a1/d1] 70 p2_0 a0,[a0/d0] 71 p1_7 int5 d15 72 p1_6 int4 d14 73 p1_5 int3 d13 74 p1_4 d12 75 p1_3 d11 76 p1_2 d10 77 p1_1 d9 78 p1_0 d8 79 p0_7 d7 80 p0_6 d6 81 p0_5 d5 82 p0_4 d4 83 p0_3 d3 84 p0_2 d2 85 p0_1 d1 86 p0_0 d0 87 p10_7 ki3 an_7 88 p10_6 ki2 an_6 89 p10_5 ki1 an_5 90 p10_4 ki0 an_4 91 p10_3 an_3 92 p10_2 an_2 93 p10_1 an_1 94 avss 95 p10_0 an_0 96 vref 97 avcc 98 p9_7 rxd4/scl4/stxd4 adtrg 99 p9_6 txd4/sda4/srxd4 anex1 100 p9_5 clk4 anex0 m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 15 of 352 rej09b0385-0100 1.5 pin functions table 1.11 pin functions (1) (100-pin package and 144-pin package) item pin name i/o type supply voltage description power supply vcc1,vcc2 vss ?? apply 3.0 to 5.5 v to pins vcc1 and vcc2, and 0 v to the vss pin. the input condition of vcc1 vcc2 must be met. analog power supply input avcc avss ? vcc1 power supply input pins to th e a/d converter and d/a converter. connect the avcc pin to vcc1, and the avss pin to vss. reset input reset i vcc1 the mcu is placed in a reset state when applying an ?l? signal to the reset pin. cnvss cnvss i vcc1 this pin switches processor mode. apply an ?h? signal to the cnvss pin to start up in microprocessor mode. external data bus width select input byte i vcc1 this pin switches data bus wid th in external memory space 3. a data bus is 16 bits wide when the byte pin is held ?l? and 8 bits wide when it is held ?h?. bus control pins d0 to d7 i/o vcc2 data (d0 to d7) input/output pins while accessing an external memory space with separate bus. d8 to d15 i/o vcc2 data (d8 to d15) inputs/output pins while accessing an external memory space with 16-bit separate bus. a0 to a22 o vcc2 address bits (a0 to a22) output pins. a23 o vcc2 inverted address bit (a23) output pin. a0/d0 to a7/d7 i/o vcc2 data (d0 to d7) input/output and 8 low-order address bits (a0 to a7) output are performed by time-sharing these pins while accessing an external memory space with multiplexed bus. a8/d8 to a15/d15 i/o vcc2 data (d8 to d15) input/output and 8 middle-order address bits (a8 to a15) output are performed by time-sharing these pins while accessing an external memory space with 16-bit multiplexed bus. cs0 to cs3 o vcc2 chip-select signal output pins used to specify external devices. wrl /wr wrh /bhe rd o vcc2 wrl , wrh , (wr , bhe ) and rd signal output pins. wrl and wrh can be switched with wr and bhe by program. ?wr l, wrh and rd are selected: if external data bus is 16 bits wide, data is written to an even address in external memory space while an ?l? is output from the wrl pin. data is written to an odd address while an ?l? is output from the wrh pin. data is read while an ?l? is output from the rd pin. ?wr , bhe and rd are selected: data is written while an ?l ? is output from the wr pin. data is read while an ?l? is output from the rd pin. data in odd address is accessed while an ?l? is output from the bhe pin. select wr , bhe and rd when an external data bus is 8 bits wide. ale o vcc2 ale signal is used for the external devices to latch address signals when the multiplexe d bus is selected. hold i vcc2 the mcu is placed in a hold state while an ?l? signal is applied to the hold pin. hlda o vcc2 the hlda pin outputs an ?l? while t he mcu is placed in a hold state rdy i vcc2 bus is placed in a wait state while an ?l? signal is applied to the rdy pin. m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 16 of 352 rej09b0385-0100 table 1.12 pin functions (2) (100-pin package and 144-pin package) item pin name i/o type supply voltage description main clock input xin i vcc1 input/output pins for the main clock oscillation circuit. connect a ceramic resonator or crystal osci llator between xin and xout. to apply an external clock, apply it to xin and leave xout open main clock output xout o vcc1 sub clock input xcin i vcc1 input/output pins for the sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout. to apply an external clock, apply it to xcin and leave xcout open. sub clock output xcout o vcc1 bclk output bclk o vcc2 bus clock output pin clock output clkout o vcc2 the clkout pin outputs the clock having the same frequency as fc, f8, or f32 int interrupt input int0 to int2 i vcc1 int interrupt input pins nt3 to int5 i vcc2 nmi interrupt input nmi i vcc1 nmi interrupt input pin. connect the nmi pin to vcc1 via a resistor when the nmi interrupt is not used. timer a ta0out to ta4out i/o vcc1 timer a0 to a4 input/output pins (ta0out is n-channel open drain output) ta0in to ta4in i vcc1 timer a0 to a4 input pins timer b tb0in to tb5in i vcc1 timer b0 to b5 input pins three-phase motor control timer output u, u , v, v , w, w o vcc1 three-phase motor control timer output pins serial interface cts0 to cts4 i vcc1 input pins to control data transmission rts0 to rts4 o vcc1 output pins to control data reception clk0 to clk4 i/o vcc1 serial clock input/output pins rxd0 to rxd4 i vcc1 serial data input pins txd0 to txd4 o vcc1 serial data output pins (txd2 is n-channel open drain output ) i 2 c mode sda0 to sda4 i/o vcc1 serial data input/output pins (sda2 is n-channel open drain output ) scl0 to scl4 i/o vcc1 serial clock input/output pins (scl2 is n-channel open drain output ) serial interface special function stxd0 to stxd4 o vcc1 serial data output pins when slave mode is selected (stxd2 is n-channel open drain output ) srxd0 to srxd4 i vcc1 serial data input pins when slave mode is selected ss0 to ss4 i vcc1 control input pins used in the serial interface special mode. m32c/8a group 1. overview rev.1.00 jul 15, 2007 page 17 of 352 rej09b0385-0100 table 1.13 pin functions (3) (100-pin package and 144-pin package) note: 1. p0 to p5 function as bus control pins and cannot be us ed as i/o ports. p1_0 to p1_7 can be used as i/o ports when using with 8-bit external bus width only. table 1.14 pin functions (4) (144-pin package only) item pin name i/o type supply voltage description reference voltage input vref i ? the vref pin supplies the reference voltage to the a/d converter and d/a converter. a/d converter an_0 to an_7 i vcc1 analog input pins for the a/d converter. adtrg i vcc1 external trigger input pin for the a/d converter. anex0 i/o vcc1 extended analog input pin for the a/d converter or output pin in external op-amp connection mode. anex1 i vcc1 extended analog input pin for the a/d converter. d/a converter da0, da1 o vcc1 output pins for the d/a converter. i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 i/o (1) vcc2 8-bit cmos i/o ports. the port pi direction register determines if each pin is used as an input po rt or an output port. the pull-up control register determines if the input ports, divided into groups of four, are pulled up or not. p6_0 to p6_7, p7_0 to p7_7, p9_0 to p9_7, p10_0 to p10_7 i/o vcc1 these 8-bit i/o ports are functionally equivalent to p0. (p7_0 and p7_1 are n-channel open drain output.) p8_0 to p8_4 p8_6, p8_7 these i/o ports are functionally equivalent to p0. input port p8_5 i vcc1 shares the pin with nmi . input port to read nmi pin level. key input interrupt input ki0 to ki3 i vcc1 key input interrupt input pins item pin name i/o type supply voltage description a/d converter an15_0 to an15_7 i vcc1 analog input pins for the a/d converter i/o ports p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 i/o vcc2 these i/o ports are functionally equivalent to p0. p14_0 to p14_6, p15_0 to p15_7 i/o vcc1 m32c/8a group 2. central processing unit (cpu) rev.1.00 jul 15, 2007 page 18 of 352 rej09b0385-0100 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the register bank is comprised of eight registers (r0, r1, r2, r3, a0, a1, sb, and fb) out of 28 cpu registers. there are two sets of register banks. figure 2.1 cpu register r0h r0l r1h r1l r2 r3 r2 r3 a0 a1 sb fb static base register (1) frame base register (1) carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved processor interrupt priority level reserved r0l r1l r2 r3 r2 r3 a0 a1 sb fb usp intb isp pc r0h r1h b31 b15 b23 b0 flg c d z s b o i u ipl b15 b0 b8 b7 svf svp vct b23 b15 b0 dmd0 dmd1 dct0 dct1 drc0 drc1 dma0 dma1 dra0 dra1 dsa0 dsa1 b23 b15 b0 b7 address registers (1) user stack pointer interrupt stack pointer interrupt table register program counter flag register general registers high-speed interrupt registers dmac-associated registers flag save register pc save register vector register dma mode registers dma transfer count registers dma transfer count reload registers dma memory address registers dma memory address reload registers dma sfr address registers note: 1. these registers comprise a register bank. there are two sets of register banks (register bank 0 and register bank 1). data registers (1) m32c/8a group 2. central processing unit (cpu) rev.1.00 jul 15, 2007 page 19 of 352 rej09b0385-0100 2.1 general registers 2.1.1 data registers (r0, r1, r2, and r3) r0, r1, r2, and r3 are 16-bit registers for transfer, arith metic and logic operations. r0 and r1 can be split into high-order (r0h/r1h) and low-order bits (r0l/r1l) to be used separately as 8-bit data registers. r0 can be combined with r2 and used as a 32-bit data register (r2r0). the same applies to r3r1. 2.1.2 address registers (a0 and a1) a0 and a1 are 24-bit registers used for a0-/a1-indir ect addressing, a0-/a1-relative addressing, transfer, arithmetic and logic operations. 2.1.3 static base register (sb) sb is a 24-bit register used for sb-relative addressing. 2.1.4 frame base register (fb) fb is a 24-bit register used for fb-relative addressing. 2.1.5 user stack pointer (usp) and interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are 24 bits wide each. the u flag is used to switch between usp and isp. refer to 2.1.8 flag register (flg) for details on the u flag. set usp and isp to even addresses to execute an interrupt sequence efficiently. 2.1.6 interrupt table register (intb) intb is a 24-bit register indicating the starting address of a relocatable interrupt vector table. 2.1.7 program counter (pc) pc is 24 bits wide and indicates the address of the next instruction to be executed. 2.1.8 flag register (flg) flg is a 16-bit register indicating the cpu state. 2.1.8.1 carry flag (c) the c flag indicates whether or no t carry or borrow has been generated after executing an instruction. 2.1.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.1.8.3 zero flag (z) the z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0. 2.1.8.4 sign flag (s) the s flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0. 2.1.8.5 register bank select flag (b) register bank 0 is selected when the b flag is set to 0. register bank 1 is selected when this flag is set to 1. 2.1.8.6 overflow flag (o) the o flag becomes 1 when an arithmetic operat ion results in an overflow; otherwise becomes 0. m32c/8a group 2. central processing unit (cpu) rev.1.00 jul 15, 2007 page 20 of 352 rej09b0385-0100 2.1.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0 and enabled when it is set to 1. the i flag becomes 0 when an interrupt request is acknowledged. 2.1.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0. usp is selected when the u flag is set to 1. the u flag becomes 0 when a hardware interrupt reque st is acknowledged or the int instruction specifying software interrupt numbers 0 to 31 is executed. 2.1.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interr upt priority levels from level 0 to level 7. if a requested interrupt has higher priority than ipl, the interrupt is enabled. 2.1.8.10 reserved space only write 0 to bits assigned to the reserved space. when read, the bits return undefined values. 2.2 high-speed interrupt registers registers associated with the hi gh-speed interrupt are follows: ? save flag register (svf) ? save pc register (svp) ? vector register (vct) refer to 11.4 high-speed interrupt for details. 2.3 dmac-associated registers registers associated with the dmac are as follows: ? dma mode register (dmd0, dmd1) ? dma transfer count register (dct0, dct1) ? dma transfer count reload register (drc0, drc1) ? dma memory address register (dma0, dma1) ? dma memory address reload register (dra0, dra1) ? dma sfr address register (dsa0, dsa1) refer to 13. dmac for details. m32c/8a group 3. memory rev.1.00 jul 15, 2007 page 21 of 352 rej09b0385-0100 3. memory figure 3.1 is a memory map of the m32c/8a group. the m32c/8a group has 16-mbyte address space from addresses 000000h to ffffffh. the fixed interrupt vectors are allocated addresses ffffdch to ffffffh. th ey store the starting address of each interrupt routine. refer to 11. interrupts for details. the internal ram is allocated higher addresses, beginn ing with address 000400h. for example, a 12-kbyte internal ram area is allocated addresses 000400h to 0033ffh. the internal ram is used not only for storing data but for the stacks when subroutines are called or wh en interrupt requests are acknowledged. sfrs are allocated address 000000h to 0003ffh. the peripheral function control registers such as for i/o ports, a/d converters, serial interfaces, timers are allocated here. all blank spaces w ithin sfrs are reserved and cannot be accessed by users. the special page vectors are allocated addresses fffe00h to ffffdbh. they are used for the jmps instruction and jsrs instruction. refer to the renesas publication m32c/80 series software manual for details. figure 3.1 memory map note: 1. the watchdog timer interr upt, oscillation stop detection interrupt , and vdet4 detection interrupt use the same vector. ffffffh special page vector table ffffdch fffe00h reset address match brk instruction overflow undefined instruction nmi watchdog timer (1) 000000h sfr internal ram reserved external space 000400h xxxxxxh 010000h ffffffh internal ram xxxxxxh 0033ffh capacity 12 kbytes 0063ffh 24 kbytes m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 22 of 352 rej09b0385-0100 4. special function registers (sfrs) special function registers (sfrs) are the control registers of peripheral functions . tables 4.1 to 4.11 list sfr address maps. table 4.1 sfr address map (1) x: undefined blank spaces are all reserved. no access is allowed. note: 1. bits pm01 and pm00 in the pm0 register maintain values set before reset, even after software reset or watchdog timer reset ha s been performed. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 (1) pm0 0000 0011b(cnvss=?h?) 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 0000 1000b 0007h system clock control register 1 cm1 0010 0000b 0008h 0009h address match interrupt enable register aier 00h 000ah protect register prcr xxxx 0000b 000bh external data bus width control register ds xxxx 1000b(byte=?l?) xxxx 0000b(byte=?h?) 000ch main clock division register mcd xxx0 1000b 000dh oscillation stop detection register cm2 00h 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00xx xxxxb 0010h address match interrupt register 0 rmad0 000000h 0011h 0012h 0013h processor mode register 2 pm2 00h 0014h address match interrupt register 1 rmad1 000000h 0015h 0016h 0017h voltage detection register 2 vcr2 00h 0018h address match interrupt register 2 rmad2 000000h 0019h 001ah 001bh voltage detection register 1 vcr1 0000 1000b 001ch address match interrupt register 3 rmad3 000000h 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h pll control register 0 plc0 0001 x010b 0027h pll control register 1 plc1 000x 0000b 0028h address match interrupt register 4 rmad4 000000h 0029h 002ah 002bh 002ch address match interrupt register 5 rmad5 000000h 002dh 002eh 002fh vdet4 detection interrupt register d4int xx00 0000b m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 23 of 352 rej09b0385-0100 table 4.2 sfr address map (2) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h address match interrupt register 6 rmad6 000000h 0039h 003ah 003bh 003ch address match interrupt register 7 rmad7 000000h 003dh 003eh 003fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h external space wait control register 0 ewcr0 x0x0 0011b 0049h external space wait control register 1 ewcr1 x0x0 0011b 004ah external space wait control register 2 ewcr2 x0x0 0011b 004bh external space wait control register 3 ewcr3 x0x0 0011b 004ch page mode wait control register 0 pwcr0 0001 0001b 004dh page mode wait control register 1 pwcr1 0001 0001b 004eh 004fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 24 of 352 rej09b0385-0100 table 4.3 sfr address map (3) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h dma0 interrupt control register dm0ic xxxx x000b 0069h timer b5 interrupt control register tb5ic xxxx x000b 006ah dma2 interrupt control register dm2ic xxxx x000b 006bh uart2 receive/ack interrupt control register s2ric xxxx x000b 006ch timer a0 interrupt control register ta0ic xxxx x000b 006dh uart3 receive/ack interrupt control register s3ric xxxx x000b 006eh timer a2 interrupt control register ta2ic xxxx x000b 006fh uart4 receive/ack interrupt control register s4ric xxxx x000b 0070h timer a4 interrupt control register ta4ic xxxx x000b 0071h uart0/uart3 bus conflict detection interrupt control register bcn0ic/bcn3ic xxxx x000b 0072h uart0 receive/ack interrupt control register s0ric xxxx x000b 0073h a/d0 conversion interrupt control register ad0ic xxxx x000b 0074h uart1 receive/ack interrupt control register s1ric xxxx x000b 0075h 0076h timer b1 interrupt control register tb1ic xxxx x000b 0077h 0078h timer b3 interrupt control register tb3ic xxxx x000b 0079h 007ah int5 interrupt control register int5ic xx00 x000b 007bh 007ch int3 interrupt control register int3ic xx00 x000b 007dh 007eh int1 interrupt control register int1ic xx00 x000b 007fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h dma1 interrupt control register dm1ic xxxx x000b 0089h uart2 transmit/nack interrupt control register s2tic xxxx x000b 008ah dma3 interrupt control register dm3ic xxxx x000b 008bh uart3 transmit/nack interrupt control register s3tic xxxx x000b 008ch timer a1 interrupt control register ta1ic xxxx x000b 008dh uart4 transmit/nack interrupt control register s4tic xxxx x000b 008eh timer a3 interrupt control register ta3ic xxxx x000b 008fh uart2 bus conflict detection interrupt control register bcn2ic xxxx x000b m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 25 of 352 rej09b0385-0100 table 4.4 sfr address map (4) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0090h uart0 transmit/nack interrupt control register s0tic xxxx x000b 0091h uart1/uart4 bus conflict detection interrupt control register bcn1ic/bcn4ic xxxx x000b 0092h uart1 transmit/nack interrupt control register s1tic xxxx x000b 0093h key input interrupt control register kupic xxxx x000b 0094h timer b0 interrupt control register tb0ic xxxx x000b 0095h 0096h timer b2 interrupt control register tb2ic xxxx x000b 0097h 0098h timer b4 interrupt control register tb4ic xxxx x000b 0099h 009ah int4 interrupt control register int4ic xx00 x000b 009bh 009ch int2 interrupt control register int2ic xx00 x000b 009dh 009eh int0 interrupt control register int0ic xx00 x000b 009fh exit priority register rlvl xxxx 0000b 00a0h 00a1h 00a2h 00a3h 00a4h 00a5h 00a6h 00a7h 00a8h 00a9h 00aah 00abh 00ach 00adh 00aeh 00afh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh 00bch 00bdh 00beh 00bfh to 02bfh m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 26 of 352 rej09b0385-0100 table 4.5 sfr address map (5) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 02c0h x0 register, y0 register x0r, y0r xxxxh 02c1h 02c2h x1 register, y1 register x1r , y1r xxxxh 02c3h 02c4h x2 register, y2 register x2r , y2r xxxxh 02c5h 02c6h x3 register, y3 register x3r , y3r xxxxh 02c7h 02c8h x4 register, y4 register x4r , y4r xxxxh 02c9h 02cah x5 register, y5 register x5r , y5r xxxxh 02cbh 02cch x6 register, y6 register x6r , y6r xxxxh 02cdh 02ceh x7 register, y7 register x7r , y7r xxxxh 02cfh 02d0h x8 register, y8 register x8r , y8r xxxxh 02d1h 02d2h x9 register, y9 register x9r , y9r xxxxh 02d3h 02d4h x10 register, y10 register x10r , y10r xxxxh 02d5h 02d6h x11 register, y11 register x11r , y11r xxxxh 02d7h 02d8h x12 register, y12 register x12r , y12r xxxxh 02d9h 02dah x13 register, y13 register x13r , y13r xxxxh 02dbh 02dch x14 register, y14 register x14r , y14r xxxxh 02ddh 02deh x15 register, y15 register x15r , y15r xxxxh 02dfh 02e0h x/y control register xyc xxxx xx00b 02e1h 02e2h 02e3h 02e4h uart1 special mode register 4 u1smr4 00h 02e5h uart1 special mode register 3 u1smr3 00h 02e6h uart1 special mode register 2 u1smr2 00h 02e7h uart1 special mode register u1smr 00h 02e8h uart1 transmit/receive mode register u1mr 00h 02e9h uart1 baud rate register u1brg xxh 02eah uart1 transmit buffer register u1tb xxxxh 02ebh 02ech uart1 transmit/receive control register 0 u1c0 0000 1000b 02edh uart1 transmit/receive control register 1 u1c1 0000 0010b 02eeh uart1 receive buffer register u1rb xxxxh 02efh m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 27 of 352 rej09b0385-0100 table 4.6 sfr address map (6) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 02f0h 02f1h 02f2h 02f3h 02f4h uart4 special mode register 4 u4smr4 00h 02f5h uart4 special mode register 3 u4smr3 00h 02f6h uart4 special mode register 2 u4smr2 00h 02f7h uart4 special mode register u4smr 00h 02f8h uart4 transmit/receive mode register u4mr 00h 02f9h uart4 baud rate register u4brg xxh 02fah uart4 transmit buffer register u4tb xxxxh 02fbh 02fch uart4 transmit/receive control register 0 u4c0 0000 1000b 02fdh uart4 transmit/receive control register 1 u4c1 0000 0010b 02feh uart4 receive buffer register u4rb xxxxh 02ffh 0300h timer b3, b4, b5 count start register tbsr 000x xxxxb 0301h 0302h timer a11 register ta11 xxxxh 0303h 0304h timer a21 register ta21 xxxxh 0305h 0306h timer a41 register ta41 xxxxh 0307h 0308h three-phase pwm control register 0 invc0 00h 0309h three-phase pwm control register 1 invc1 00h 030ah three-phase output buffer register 0 idb0 xx11 1111b 030bh three-phase output buffer register 1 idb1 xx11 1111b 030ch dead time timer dtt xxh 030dh timer b2 interrupt generation frequency set counter ictb2 xxh 030eh 030fh 0310h timer b3 register tb3 xxxxh 0311h 0312h timer b4 register tb4 xxxxh 0313h 0314h timer b5 register tb5 xxxxh 0315h 0316h 0317h 0318h 0319h 031ah 031bh timer b3 mode register tb3mr 00xx 0000b 031ch timer b4 mode register tb4mr 00xx 0000b 031dh timer b5 mode register tb5mr 00xx 0000b 031eh 031fh external interrupt source select register ifsr 00h m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 28 of 352 rej09b0385-0100 table 4.7 sfr address map (7) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 0320h 0321h 0322h 0323h 0324h uart3 special mode register 4 u3smr4 00h 0325h uart3 special mode register 3 u3smr3 00h 0326h uart3 special mode register 2 u3smr2 00h 0327h uart3 special mode register u3smr 00h 0328h uart3 transmit/receive mode register u3mr 00h 0329h uart3 baud rate register u3brg xxh 032ah uart3 transmit buffer register u3tb xxxxh 032bh 032ch uart3 transmit/receive control register 0 u3c0 0000 1000b 032dh uart3 transmit/receive control register 1 u3c1 0000 0010b 032eh uart3 receive buffer register u3rb xxxxh 032fh 0330h 0331h 0332h 0333h 0334h uart2 special mode register 4 u2smr4 00h 0335h uart2 special mode register 3 u2smr3 00h 0336h uart2 special mode register 2 u2smr2 00h 0337h uart2 special mode register u2smr 00h 0338h uart2 transmit/receive mode register u2mr 00h 0339h uart2 baud rate register u2brg xxh 033ah uart2 transmit buffer register u2tb xxxxh 033bh 033ch uart2 transmit/receive control register 0 u2c0 0000 1000b 033dh uart2 transmit/receive control register 1 u2c1 0000 0010b 033eh uart2 receive buffer register u2rb xxxxh 033fh 0340h count start register tabsr 00h 0341h clock prescaler reset register cpsrf 0xxx xxxxb 0342h one-shot start register onsf 00h 0343h trigger select register trgsr 00h 0344h up/down select register udf 00h 0345h 0346h timer a0 register ta0 xxxxh 0347h 0348h timer a1 register ta1 xxxxh 0349h 034ah timer a2 register ta2 xxxxh 034bh 044ch timer a3 register ta3 xxxxh 034dh 034eh timer a4 register ta4 xxxxh 034fh m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 29 of 352 rej09b0385-0100 table 4.8 sfr address map (8) x: undefined blank spaces are all rese rved. no access is allowed. note: 1. the tcspr register maintains values set before reset, even after software reset or watchdog timer reset has been performed. address register symbol after reset 0350h timer b0 register tb0 xxxxh 0351h 0352h timer b1 register tb1 xxxxh 0353h 0354h timer b2 register tb2 xxxxh 0355h 0356h timer a0 mode register ta0mr 00h 0357h timer a1 mode register ta1mr 00h 0358h timer a2 mode register ta2mr 00h 0359h timer a3 mode register ta3mr 00h 035ah timer a4 mode register ta4mr 00h 035bh timer b0 mode register tb0mr 00xx 0000b 035ch timer b1 mode register tb1mr 00xx 0000b 035dh timer b2 mode register tb2mr 00xx 0000b 035eh timer b2 special mode register tb2sc xxxx xxx0b 035fh count source prescaler register (1) tcspr 0xxx 0000b 0360h 0361h 0362h 0363h 0364h uart0 special mode register 4 u0smr4 00h 0365h uart0 special mode register 3 u0smr3 00h 0366h uart0 special mode register 2 u0smr2 00h 0367h uart0 special mode register u0smr 00h 0368h uart0 transmit/receive mode register u0mr 00h 0369h uart0 baud rate register u0brg xxh 036ah uart0 transmit buffer register u0tb xxxxh 036bh 036ch uart0 transmit/receive control register 0 u0c0 0000 1000b 036dh uart0 transmit/receive control register 1 u0c1 0000 0010b 036eh uart0 receive buffer register u0rb xxxxh 036fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h dma0 request source select register dm0sl 0x00 0000b 0379h dma1 request source select register dm1sl 0x00 0000b 037ah dma2 request source select register dm2sl 0x00 0000b 037bh dma3 request source select register dm3sl 0x00 0000b 037ch crc data register crcd xxxxh 037dh 037eh crc input register crcin xxh 037fh m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 30 of 352 rej09b0385-0100 table 4.9 sfr address map (9) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 0380h a/d0 register 0 ad00 00xxh 0381h 0382h a/d0 register 1 ad01 00xxh 0383h 0384h a/d0 register 2 ad02 00xxh 0385h 0386h a/d0 register 3 ad03 00xxh 0387h 0388h a/d0 register 4 ad04 00xxh 0389h 038ah a/d0 register 5 ad05 00xxh 038bh 038ch a/d0 register 6 ad06 00xxh 038dh 038eh a/d0 register 7 ad07 00xxh 038fh 0390h 0391h 0392h a/d0 control register 4 ad0con4 xxxx 00xxb 0393h 0394h a/d0 control register 2 ad0con2 xx0x x000b 0395h a/d0 control register 3 ad0con3 xxxx x000b 0396h a/d0 control register 0 ad0con0 00h 0397h a/d0 control register 1 ad0con1 00h 0398h d/a register 0 da0 xxh 0399h 039ah d/a register 1 da1 xxh 039bh 039ch d/a control register dacon xxxx xx00b 039dh 039eh 039fh m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 31 of 352 rej09b0385-0100 table 4.10 sfr address map (10) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. these registers cannot be used in the 100-pin package. 2. set to ffh in the 100-pin package. address register address register 03a0h 03a1h 03a2h 03a3h 03a4h 03a5h 03a6h 03a7h 03a8h 03a9h 03aah 03abh 03ach 03adh 03aeh 03afh function select register c psc 00x0 0000b 03b0h function select register a0 ps0 00h 03b1h function select register a1 ps1 00h 03b2h function select register b0 psl0 00h 03b3h function select register b1 psl1 00h 03b4h function select register a2 ps2 00x0 0000b 03b5h function select register a3 ps3 00h 03b6h function select register b2 psl2 00x0 0000b 03b7h function select register b3 psl3 00h 03b8h 03b9h 03bah 03bbh 03bch 03bdh 03beh 03bfh 03c0h port p6 register p6 xxh 03c1h port p7 register p7 xxh 03c2h port p6 direction register pd6 00h 03c3h port p7 direction register pd7 00h 03c4h port p8 register p8 xxh 03c5h port p9 register p9 xxh 03c6h port p8 direction register pd8 00x0 0000b 03c7h port p9 direction register pd9 00h 03c8h port p10 register p10 xxh 03c9h port p11 register (1) p11 xxh 03cah port p10 direction register pd10 00h 03cbh port p11 direction register (1)(2) pd11 xxx0 0000b 03cch port p12 register (1) p12 xxh 03cdh port p13 register (1) p13 xxh 03ceh port p12 direction register (1)(2) pd12 00h 03cfh port p13 direction register (1)(2) pd13 00h m32c/8a group 4. special function registers (sfrs) rev.1.00 jul 15, 2007 page 32 of 352 rej09b0385-0100 table 4.11 sfr address map (11) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. these registers cannot be used in the 100-pin package. 2. set to ffh in the 100-pin package. 3. set to 00h in the 100-pin package. address register address register 03d0h port p14 register (1) p14 xxh 03d1h port p15 register (1) p15 xxh 03d2h port p14 direction register (1)(2) pd14 x000 0000b 03d3h port p15 direction register (1)(2) pd15 00h 03d4h 03d5h 03d6h 03d7h 03d8h 03d9h 03dah pull-up control register 2 pur2 00h 03dbh pull-up control register 3 pur3 00h 03dch pull-up control register 4 (1)(3) pur4 xxxx 0000b 03ddh 03deh 03dfh 03e0h port p0 register p0 xxh 03e1h port p1 register p1 xxh 03e2h port p0 direction register pd0 00h 03e3h port p1 direction register pd1 00h 03e4h port p2 register p2 xxh 03e5h port p3 register p3 xxh 03e6h port p2 direction register pd2 00h 03e7h port p3 direction register pd3 00h 03e8h port p4 register p4 xxh 03e9h port p5 register p5 xxh 03eah port p4 direction register pd4 00h 03ebh port p5 direction register pd5 00h 03ech 03edh 03eeh 03efh 03f0h pull-up control register 0 pur0 00h 03f1h pull-up control register 1 pur1 xxxx 0000b 03f2h 03f3h 03f4h 03f5h 03f6h 03f7h 03f8h 03f9h 03fah 03fbh 03fch 03fdh 03feh 03ffh port control register pcr xxxx xxx0b m32c/8a group 5. reset rev.1.00 jul 15, 2007 page 33 of 352 rej09b0385-0100 5. reset hardware reset 1, hardware reset 2 (vdet3 detection function), software reset and watchdog timer reset are implemented to reset the mcu. 5.1 hardware reset 1 pins, cpu, and sfrs are reset by using the reset pin. when a low-level (?l?) signal is applied to the reset pin while the supply voltage meets the recommended operating conditions, ports and i/o pins for peripheral functions are reset. (refer to table 5.1 pin states while reset pin is held ?l? .) also, the oscillation circuit is reset and the main clock starts oscillating. cpu and sfrs are reset when th e signal applied to the reset pin changes from ?l? to high-level (?h?), and th en the mcu executes a program beginning with the address indicated by the reset vector. the wdc5 bit in the wdc register and the internal ram are not reset by hardwa re reset 1. when an ?l? signal is applied to the reset pin while writing data to the internal ram, the value written to the internal ram becomes undefined. figure 5.1 shows an example of the reset circuit. figure 5.2 shows a reset sequence. table 5.1 lists pin states while the reset pin is held ?l?. 5.1.1 reset at a stab le supply voltage (1) apply an ?l? signal to the reset pin. (2) input 20 clock cycles or more into the xin pin. (3) apply an ?h? signal to the reset pin. 5.1.2 power-on reset (1) apply an ?l? signal to the reset pin. (2) increase the supply voltage until it meets the recommended operating condition. (3) wait for td(p-r) (internal power supply stabilization time) or more to allow the internal power supply to stabilize. (4) inputs 20 clock cycles or more into the xin pin. (5) apply an ?h? signal to the reset pin. figure 5.1 example of reset circuit vcc1 reset 0v vcc1 0v reset recommended operating volatage 0.2vcc1 or below input td(p-r) + 20 clock cycles or more to the xin pin 0.2vcc1 or below note: 1. if operating at vcc1 > vcc2, vcc2 voltage must be lower than vcc1 voltage when powering up and down. m32c/8a group 5. reset rev.1.00 jul 15, 2007 page 34 of 352 rej09b0385-0100 figure 5.2 reset sequence 40 to 45 bclk cycles ffffffh microprocessor mode byte = "h" content of reset vector h l fffffch fffffdh fffffeh h l h l fffffch h l fffffeh content of reset vector h l h l address a23 rd wr address microprocessor mode byte = "l" a23 rd wr vcc1, vcc2 xin reset bclk 20 or more clock cycles are required td(p-r) ms or more is required m32c/8a group 5. reset rev.1.00 jul 15, 2007 page 35 of 352 rej09b0385-0100 table 5.1 pin states while reset pin is held ?l? (2) notes: 1. ports p11 to p15 are provided in the 144-pin package only. 2. the availability of the pull-up re sistors is undefined until the inte rnal supply voltage stabilizes. 3. these pin states are defined after the power is turned on and the internal supply voltage stabilizes. until then, the pin states are undefined. 5.2 hardware reset 2 (vde t3 detection function) pins, cpu, and sfrs are reset by the vdet3 detection function, when the voltage applied to the vcc1 pin drops to vdet3 (v) or below. the states of the pins, cpu, and sfrs after reset are the same as the hardware reset 1. refer to 6. power supply voltage detection function for details on vdet3 detection function. 5.3 software reset when the pm03 bit in the pm0 register is set to 1 (mcu is reset), the mcu resets the cpu, sfrs, ports, and i/o pins for peripheral functions. and then the mcu executes a program in an address i ndicated by the reset vector. set the pm03 bit to 1 while the main clock is selected as the clock source for the cpu clock and the main clock oscillation is stable. the software reset does not re set the following sfrs; bits pm01 and pm11 in the pm0 register, the wdc5 bit in the wdc register, and the tcspr register. processor mode remains unchanged since bits pm01 and pm00 are not reset. 5.4 watchdog timer reset when the cm06 bit in the cm0 register is set to 1 (reset) and the watchdog timer underflows, the mcu resets the cpu, sfrs, ports, and i/o pins for peripheral functions . and then the mcu executes a program in an address indicated by the reset vector. the watchdog timer reset does not reset the following sfrs ; bits pm01 and pm11 in the pm0 register, the wdc5 bit in the wdc register, and the tcspr register. processor mode remains unchanged since bits pm01 and pm00 are not reset. pin name microprocessor mode cnvss = ?h? byte = ?l? byte = ?h? p0 data input (high-impedance) p1 data input (high-impedance) input port (high-impedance) p2 to p4 address output (undefined) p5_0 wr signal output (?h?) (3) p5_1 bhe signal output (?h?) p5_2 rd signal output (?h?) (3) p5_3 bclk output (3) p5_4 hlda signal output (output level depends on an input level to the hold pin) (3) p5_5 hold signal input (high-impedance) p5_6 ?h? signal output (3) p5_7 rdy signal input (high-impedance) p6 to p15 (1) input port (high-impedance) m32c/8a group 5. reset rev.1.00 jul 15, 2007 page 36 of 352 rej09b0385-0100 5.5 internal registers figure 5.3 shows cpu register states after reset. refer to 4. special function registers (sfrs) for sfr states after reset. figure 5.3 cpu register states after reset data register (r0h/r0l) data register (r1h/r1l) data register (r2) data register (r3) address register (a0) address register (a1) static base register (sb) frame base register (fb) r0h r0l r1h r1l r2 r3 a0 a1 sb fb 00h 00h 0000h 0000h 000000h 000000h 000000h 000000h 000000h 000000h 000000h contents of addresses fffffeh to fffffch 00h 00h b15 b23 b0 0 0 0 0 0 0 0 0 x b15 b0 b8 b7 xxxxh xxxxxxh xxxxxxh b23 b15 b0 00h 00h xxxxh xxxxh xxxxh xxxxh xxxxxxh xxxxxxh xxxxxxh xxxxxxh xxxxxxh xxxxxxh b23 b15 b0 b7 general registers x x x x 0 0 0 uiobszdc ipl 0: 0 after reset x: undefined after reset b0 b15 user stack pointer (usp) interrupt stack pointer (isp) interrupt table register (intb) flag register (flg) high-speed interrupt registers dmac-associated registers flag save register (svf) pc save register (svp) vector register (vct) dma mode register (dmd0) dma mode register (dmd1) dma transfer count register (dct0) dma transfer count register (dct1) dma transfer count reload register (drc0) dma transfer count reload register (drc1) dma memory address register (dma0) dma memory address register (dma1) dma memory address reload register (dra0) dma memory address reload register (dra1) dma sfr address register (dsa0) dma sfr address register (dsa1) program counter (pc) m32c/8a group 6. power supply voltage detection function rev.1.00 jul 15, 2007 page 37 of 352 rej09b0385-0100 6. power supply voltage detection function the power supply voltage detection function has the vdet 3 detection function, vdet4 detection function, and cold start/warm start determination function. the vdet3 detecti on function and vdet4 detection function detect the changes in voltage and trigger the events. the cold start/warm st art determination function determines whether the mcu is reset at power-on or reset while running. the power supply voltage detection function is available only with vcc1 = 4.2v to 5.5v standard. figure 6.1 shows a block diagram of the voltage detection ci rcuit. figures 6.2 to 6.4 show voltage detection-associated registers. figure 6.1 power supply voltage detection function block diagram cpu clock 1/2 digital filter watchdog timer interrupt signal vdet4 detection interrupt signal oscillation stop detection interrupt signal watchdog timer interrupt request vdet3 detection fucntion 00b 01b 10b 11b df1 to df0 1/2 1/2 1/8 (rejection range: 200 ns) d40 d42 bit cm10: bit in the cm1 register vc13: bit in the vcr1 register vc26, vc27: bits in the vcr2 register df1 and df0, d40, d41, d42: bits in the d4int register wdc5: bit in the wdc register note: 1. when the vc27 bit in the v cr2 register is set to 0 (vde t4 detection function not used), the vdet4 detection signal bec omes "h". wdc5 s r q write a given value to the wdc register cold/warm (cold start, warm start) hardware reset 1 at power-on e 1 shot t analog filter internal reset signal (active "l") wait time to release hardware reset 2: td(s-r) q vcc1 vc26 vc27 vdet4 detection signal (1) e vc13 cold start/warm start determination function vdet4 detection function cm10 latch cm10 wait instruction (wait mode) d41 vdet3 vdet3 output one-shot pulse when the d42 bit becomes 0 to 1. m32c/8a group 6. power supply voltage detection function rev.1.00 jul 15, 2007 page 38 of 352 rej09b0385-0100 figure 6.2 vcr1 register, vcr2 register b7 0 0 0 0 0 b6 b5 b4 b1 b2 b3 voltage detection register 1 symbol vcr1 address 001bh bit symbol bit name rw ? (b2-b0) after reset 0000 1000b rw b0 function ro note: 1. the vc13 bit is enabled when the vc27 bit in the vc r2 register is set to 1 (vdet4 detection function used). the vc13 bit becomes 1 when the vc27 bit is set to 0 (vdet4 detection function not used). vc13 voltage change monitor flag (1) 0: vcc1 < vdet4 1: vcc1 vdet4 ? (b7-b4) reserved bits set to 0 rw 0 0 reserved bits set to 0 b7 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 voltage detection register 2 (1) symbol vcr2 address 0017h bit symbol bit name rw ? (b5-b0) after reset 00h rw b0 function rw vc26 vdet3 detection function select bit (2, 4, 5) 0: vdet3 detection function not used 1: vdet3 detection function used vc27 vdet4 detection function select bit (3, 4) 0: vdet4 detection function not used 1: vdet4 detection function used rw reserved bits set to 0 notes: 1. set the vcr2 register after the prc3 bi t in the prcr register is set to 1 (write enable). 2. to use the hardware reset 2 (vdet3 detection function), set the vc26 bit to 1. 3. to use the vdet4 detection function, set the vc27 bit to 1 and the d40 bit in the d4int register to 1 (vdet4 detection i nterrupt used). the vc13 bit in the vcr1 register and the d42 bit in the d4int register are enabled when the vc27 bit is set to 1. 4. after the vc26 or vc27 bit is set to 1, the detection circuit waits for td(e-a) to elapse before starting operation. 5. the vc26 bit is disabled when the mcu is in stop mode. (the hardware reset 2 is not performed even if the voltage appli ed to the vcc1 pin drops below vdet3.) m32c/8a group 6. power supply voltage detection function rev.1.00 jul 15, 2007 page 39 of 352 rej09b0385-0100 figure 6.3 d4int register b7 b6 b5 b4 b1 b2 b3 vdet4 detection interrupt register (1) symbol d4int address 002fh bit symbol bit name rw d40 after reset xx00 0000b rw b0 function vdet4 detection interrupt enable bit (2) d41 rw rw 0: vdet4 detection interrupt is not used to exit wait/stop mode 1: vdet4 detection interrupt is used to exit wait/stop mode wait mode/stop mode exit control bit (3) 0: vdet4 detection interrupt disabled 1: vdet4 detection interrupt enabled d42 voltage change detect flag (4, 5) 0: not detected 1: voltage crosses vdet4 d43 wdt underflow detect flag (5) 0: not detected 1: detected df0 df1 unimplemented. read as undefined value. sampling clock select bits b5 b4 0 0: cpu clock divided-by-8 0 1: cpu clock divided-by-16 1 0: cpu clock divided-by-32 1 1: cpu clock divided-by-64 rw rw ? rw ? (b7-b6) notes: 1. set the d4int register aft er the prc3 bit in the prcr re gister is set to 1 (write enable). 2. use the following procedur e to set the d40 bit to 1: (1) set the vc27 bit in the vcr2 register to 1 (2) wait fo r td(e-a) before the voltage detection c ircuit starts operating (3) wait fo r required sampling time (see table "sampling period" ) (4) set the d40 bit to 1 3. if the vdet4 detection int errupt has been used to exit w ait mode or stop mode, set the d41 bit to 0 and then set it to 1 to use the vdet4 detection i nterrupt again to exit these modes. 4. the d42 bit is enabled when the vc27 bit is set to 1 (vd et4 detection function used ). the d42 bit becomes 0 when the v c27 bit is set to 0 (vdet4 detection function not used). 5. the d43 bit can be set to 0 by program. writing a 0 has no effect. m32c/8a group 6. power supply voltage detection function rev.1.00 jul 15, 2007 page 40 of 352 rej09b0385-0100 figure 6.4 wdc register b7 b6 b5 b4 b1 b2 b3 watchdog timer control register symbol wdc address 000fh bit symbol bit name rw ? (b4-b0) after reset 00xx xxxxb ro b0 function rw note: 1. the wdc5 bit is 0 after power-on. it can be set to 1 only by program. the bit becomes 1 by writing either a 0 or 1. the bit remains a value set before reset, even after reset has been performed. high-order bits of watchdog timer wdc5 cold start/warm start determine flag (1) 0: cold start 1: warm start ? (b6) reserved bit set to 0 rw 0 rw wdc7 prescaler select bit 0: divide-by-16 1: divide-by-128 m32c/8a group 6. power supply voltage detection function rev.1.00 jul 15, 2007 page 41 of 352 rej09b0385-0100 6.1 vdet3 detection function the hardware reset 2 is performed if the voltage applied to the vcc1 pin drops to vdet3 (v) or below. set the vc26 bit in the vcr2 register to 1 to use this vdet3 detection function. when the hardware reset 2 occurs, ports and i/o pins for peripheral functions are reset. the cpu and sfrs are reset when td(s-r) elapses after the voltage applied to th e vcc1 pin reaches vdet3r (v ) or above. then, the mcu executes a program in an address indicated by the reset vector. the states of pins a nd sfrs after reset are the same as the hardware reset 1. use the vdet3 detection function while operating at or ab ove vdet3s. if the applied voltage drops below vdet3s, perform the hardware reset 1 (refer to 5.1.1 reset at a stable supply voltage ). the vdet3 detection function cannot be used while the mcu is in stop mode. figure 6.5 shows a vdet3 detection function operation example. figure 6.5 vdet3 detection function operation example vss vcc1 reset set to 1 (vdet3 detection function used) by program. notes: 1. typical value. 2. minimum value. 5.0 v 5.0 v vdet3r vdet3 vdet3s 2.0v (2) undefined vc26 bit in the vcr2 register internal reset signal 3.0 v (1) 3.1 v (1) h l 1 0 h l wait time to release hardware reset 2: td(s-r) m32c/8a group 6. power supply voltage detection function rev.1.00 jul 15, 2007 page 42 of 352 rej09b0385-0100 6.2 vdet4 detection function vdet4 detection interrupt is generated if the voltage applie d to the vcc1 pin crosses the vdet4 (v) level, either by dropping below or by rising above vdet4. set the vc27 bit in the vcr2 register to 1 (vdet4 detection function used) and the d40 bit in the d4int register to 1 (vdet4 detection interrupt enabled) to use the vdet4 detection function. the d42 bit becomes 1 (voltage crosses vdet4) as soon as the applied voltage crosse s vdet4. when the d42 bit changes from 0 to 1, a vdet4 detection interrupt request is generated. the d42 bit does not become 0 automatically when the interrupt is acknowledged. set it to 0 (not detected) by program. whether the voltage has dropped below vdet4 or risen above vdet4 can be determined by reading the vc13 bit in the vcr1 register. set the d41 bit in the d4int register to 1 to use the vdet 4 detection interrupt to exit wait mode or stop mode. the mcu exits wait mode or stop mode if the vdet4 det ection signal is generated even if the d42 bit is 1. the vdet4 detection interrupt shares the same interrupt vector with watchdog timer interrupt and oscillation stop detection interrupt. when using the vdet4 detection inte rrupt simultaneously with these interrupts, determine whether the vdet4 detection interrupt is generated by reading the d42 bit in the interrupt routine. table 6.1 shows conditions to generate vdet4 detecti on interrupt request. figure 6.6 shows a vdet4 detection function operation example. bits df1 and df0 in the d4int register determine the sampling clock which is used to detects if the voltage applied to the vcc1 pin crosses vdet4. table 6.2 shows the sampling periods. ? : either 0 or 1 notes: 1. set to 0 by program before generating an interrupt. 2. an interrupt request is generated when the sampling period elapses after the value of the bit is changed. see figure 6.6 vdet4 detection function operation example for details. 3. cpu operating mode includes main clock mode, pl l mode, low speed mode, low-power consumption mode, on-chip oscillator mode, on-chip oscillator low-power consumption mode. (refer to 9. clock generation circuits .) 4. refer to 6.2.1 usage notes on vdet4 detection interrupt . note: 1. set the cpu clock below 24 mhz to use the voltage detection function. table 6.1 conditions to generate vdet4 detection interrupt request operating mode vc27 bit d40 bit d41 bit d42 bit (1) vc13 bit (2) cpu operating mode (3) 11 ? 0 to 1 0 to 1 1 to 0 wait mode, stop mode (4) 1 ? 0 to 1 table 6.2 sampling periods cpu clock (mhz) sampling clock ( s) divided-by-8 divided-by-16 divided-by-32 divided-by-64 16 3.0 6.0 12.0 24.0 24 2.0 4.0 8.0 16.0 m32c/8a group 6. power supply voltage detection function rev.1.00 jul 15, 2007 page 43 of 352 rej09b0385-0100 figure 6.6 vdet4 detection function operation example voltage applied to vcc1 time sampling period reset vc27 bit vc13 bit output from digital filter d42 bit vdet4 detection interrupt request signal from d42 bit vdet4 detection interrupt request signal when d41 bit is 1 notes: 1. apply an "l" to the reset pin when the voltage input to the vcc1 pin drops to 3.0 v or below. when the voltage rises above 3.0 v, and the voltage of the internal vdc and the main clock oscillation stabilize, apply an "h" to the reset pin. 2. when the d42 bit is set to 1, the vdet4 detection inter rupt request signal is not generated even if the vdet4 detection signal is output from the digital filter. 3. if the vdet4 detection interrupt has been used to exit wait mode or stop mode, set the d41 bit to 0 and then set it back to 1 to use the vdet4 detection interrupt again to exit wait/stop mode. vdet4 (v) 3 (v) (note 1) h l 1 0 1 0 h l 1 0 h l 1 0 d41 bit h l (note 2) (note 3) vc27 bit: bit in the vcr2 register vc13 bit: bit in the vcr1 register vc41 bit, vc42 bit: bits in the d4int register m32c/8a group 6. power supply voltage detection function rev.1.00 jul 15, 2007 page 44 of 352 rej09b0385-0100 6.2.1 usage notes on vdet4 detection interrupt when all the conditions below are met, the vdet4 detection interrupt is generated and the mcu exits wait mode as soon as the wait instruction is executed or exits st op mode as soon as the cm10 bit in the cm1 register is set to 1 (all clocks stopped). ? the vc27 bit in the vcr2 register is set to 1 (vdet4 detection function used) ? the d40 bit in the d4int register is set to 1 (vdet4 detection interrupt enabled) ? the d41 bit in the d4int register is set to 1 (vdet4 detection interrupt is used to exit wait/stop mode) ? the voltage applied to the vcc1 pin is vdet4 or above (the vc13 bit in the vcr1 register is 1) execute the wait instruction or set the cm10 bit to 1 (all clocks stopped) while the vc13 bit is 0 (vcc1 < vdet4), if the mcu is configured to enter wa it/stop mode when voltage applied to the vcc1 pin drops vdet4 or below and to exit wait/stop mode when the voltage applied rises to vdet4 or above. if the vdet4 detection interrupt has been used to exit wa it mode or stop mode, set the d41 bit to 0 and then set it back to 1 to use the vdet4 detection interrupt again to exit wait/stop mode. 6.3 cold start/warm start determine function the wdc5 bit in the wdc register dete rmines whether it is a reset process wh en power-on (cold start) or a reset process when the reset signal is input during mcu running (warm start). default value of the wdc5 bit is 0 (cold start) when power-on, and the bit is set to 1 (war m start) by writing given values to the wdc register. the wdc5 bit does not become 0 even if the hardware reset 1, hardware reset2, software reset, or watchdog timer reset is performed. figure 6.7 shows an example of cold start/warm start determine function operation. figure 6.7 cold start/warm start determine function operation the wdc5 bit remains set to 1 even if voltage applied to reset becomes 0 v. t2 program starts running t1 pch transistor on (approx. 4 v) cpu comes out of reset set to 1 by program t > 100 s 5 v 0 v 5 v 0 v 1 0 vcc1 wdc5 bit reset reset sequence (approx.20 s@16 mhz) note: 1. if the time difference between t1 and t2 is greater, it may take longer to set the wdc5 bit to 1. m32c/8a group 7. processor mode rev.1.00 jul 15, 2007 page 45 of 352 rej09b0385-0100 7. processor mode 7.1 processor mode microprocessor mode can be selected as the processor mode. table 7.1 lists the features of the processor mode. table 7.1 processor mode features note: 1. refer to 8. bus for details. 7.2 setting of processor mode input an ?h? signal to the cn vss pin and release the reset signal to start up in microprocessor mode. bits pm01 and pm00 are set to 11b (microprocessor mode) af ter reset. do not set to values other than 11b. figures 7.1 and 7.2 show the pm0 register and pm1 register. figure 7.3 shows a memory map in microprocessor mode. processor mode accessible space pins assigned to i/o port microprocessor mode (1) sfr, internal ram, external space p0 to p5 become bus control pins m32c/8a group 7. processor mode rev.1.00 jul 15, 2007 page 46 of 352 rej09b0385-0100 figure 7.1 pm0 register b7 1 1 b6 b5 b4 b1 b2 b3 processor mode register 0 (1) symbol pm0 address 0004h bit symbol bit name rw pm00 after reset 0000 0011b ( cnvss = "h") rw b0 function processor mode bits (2) pm01 rw b1 b0 1 1: microprocessor mode do not set to values other than the above. pm02 r/w mode select bit 0: rd/bhe/wr 1: rd/wrh/wrl pm03 software reset bit the mcu is reset when this bit is set to 1. read as 0. pm04 pm05 reserved bit set to 0 multiplexed bus space select bits (3) b5 b4 0 0: multiplexed bus is not used 0 1: access the cs2 area using multiplexed bus 1 0: access the cs1 area using multiplexed bus 1 1: do not set to this value. ` (b6) rw rw rw 0 rw rw bclk output function select bit 0: bclk output (4) 1: no bclk output pm07 rw notes: 1. set the pm0 register after the prc1 bit in the prcr register is set to 1 (write enable). 2. bits pm01 and pm00 maintain v alues set before reset, even after software reset or watchdog timer reset has performed. 3. the pm05 and pm04 bits setti ng is enabled in microproce ssor mode. set these bits in the combination with bits pm11 an d pm10 in the pm 1 register. refer to the table "multiplexed bus settings and chip-select areas " in the bus chapter. 4. to output bclk from p5_3 in microprocessor mode, set the pm07 bit to 0, bits cm01 and cm00 in the cm0 register to "00b" (i/o port p5_3), and bits pm15 and pm14 in the pm1 register to 00b, 10b, or 11b. m32c/8a group 7. processor mode rev.1.00 jul 15, 2007 page 47 of 352 rej09b0385-0100 figure 7.2 pm1 register b7 b6 b5 b4 b1 b2 b3 processor mode register 1 (1) symbol pm1 address 0005h bit symbol bit name rw pm10 rw b0 function external space mode bits pm11 rw b1 b0 0 0: mode 0 (a20 to a23 for p4_4 to p4_7) 0 1: mode 1 (a20 for p4_4, cs2 to cs0 for p4_5 to p4_7) 1 0: mode 2 (a20 and a21 for p4_4 and p4_5, cs1 and cs0 fo r p4_6 and p4_7) 1 1: mode 3 (cs3 to cs0 for p4_4 to p4_7) pm12 internal memory wait bit 0: no wait state 1: 1 wait state pm13 sfr area wait bit pm14 pm15 reserved bits set to 0 ale pin select bits b5 b4 0 0: no ale 0 1: p5_3 (2) 1 0: p5_6 1 1: p5_4 ? (b7-b6) rw rw rw 0 0 rw rw 0: 1 wait state 1: 2 wait states after reset 00h notes: 1. set the pm1 register after the prc1 bi t in the prcr register is set to 1 (write enable). 2. to output ale signal from p5_3, set bits pm15 and pm14 to 01b, and bits cm01 and cm00 in the cm0 register to 00b (i/o p ort p5_3). m32c/8a group 7. processor mode rev.1.00 jul 15, 2007 page 48 of 352 rej09b0385-0100 figure 7.3 memory map in microprocessor mode cs area controlled by the ewcri register: cs0 controlled by ewcr3 cs1 controlled by ewcr0 cs2 controlled by ewcr1 cs3 controlled by ewcr2 notes: 1. 200000h to 010000h = 1984 kbytes . 64k bytes less than 2 m bytes. 2. 400000h to 010000h = 4032 kbytes . 64k bytes less than 4 m bytes. 000000h 000400h c00000h d00000h e00000h f00000h ffffffh 010000h 100000h 200000h 300000h 400000h sfr internal ram external space 3 external space 2 sfr internal ram not used cs0 2-mbyte external space 3 not used sfr internal ram not used cs0 4-mbyte external space 3 sfr internal ram not used cs3 1-mbyte external space 2 not used cs0 1-mbyte external space 3 mode 0 mode 1 mode 2 mode 3 external space 0 external space 1 cs1 2-mbyte external space 0 (1) cs2 2-mbyte external space 1 cs1 4-mbyte external space 0 (2) not used cs1 1-mbyte external space 0 cs2 1-mbyte external space 1 reserved reserved reserved reserved microprocessor mode m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 49 of 352 rej09b0385-0100 8. bus in microprocessor mode, the following pins become bus control pins: d0 to d15, a0 to a22, a23 , cs0 to cs3 , wrl / wr , wrh /bhe , rd , clkout/bclk/ale, hlda /ale, hold , ale, rdy . 8.1 bus settings bus setting is determined by the byte pin, the ds register, the pm05 and pm04 bits in the pm0 register, and bits pm11 and pm10 in the pm1 register. table 8.1 lists how to change bus settings. figure 8.1 shows the ds register. table 8.1 bus settings figure 8.1 ds register bus setting pin & registers used for setting selecting external data bus width ds register setting bus width after reset byte pin (for external space 3 only) selecting separate bus or multiplexed bus bits pm05 and pm04 in the pm0 register number of chip-select pins bits pm11 and pm10 in the pm1 register b7 b6 b5 b4 b1 b2 b3 external data bus wi dth control register symbol ds address 000bh bit symbol bit name rw after reset xxxx 1000b (byte pin = "l") xxxx 0000b (byte pin = "h") b0 function ds0 rw ds1 ds2 ds3 ? (b7-b4) rw rw rw ? external space 0 data bus width select bit external space 1 data bus width select bit 0: 8 bits wide 1: 16 bits wide external space 2 data bus width select bit external space 3 data bus width select bit (1) 0: 8 bits wide 1: 16 bits wide 0: 8 bits wide 1: 16 bits wide 0: 8 bits wide 1: 16 bits wide unimplemented. write 0. read as undefined value. m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 50 of 352 rej09b0385-0100 8.1.1 selecting external address bus the number of external address bus pins, the number of chip-select pins, and chip -select-assigned address space (cs area) vary in each external space mode. bits pm11 and pm10 in the pm1 register select external space mode. 8.1.2 selecting external data bus the ds register selects either external 8-bit data bus or 16-bit data bus per each external space. the data bus in the external space 3, after reset, becomes 16 bits wide when a low-level (?l?) signal is applied to the byte pin and 8 bits wide when a high-level (?h?) signal is applied. keep the byte pin level while the mcu is operating. internal bus is always 16 bits wide. 8.1.3 selecting separa te/multiplexed bus bits pm05 and pm04 in the pm0 register select either th e separate bus or multiplexe d bus. the mcu starts up with the separate bus after reset. 8.1.3.1 separate bus with the separate bus format, the mcu performs data input/output and address output using individual buses. the ds register selects 8-bit or 16-bit external data bus for each external space. if all dsi bits in the ds register (i = 0 to 3) are set to 0 (8-bit data bus), port p0 functi ons as the data bus and port p1 as the programmable i/o port. if any of the dsi bits is set to 1 (16- bit data bus), ports p0 and p1 function as the data bus. port p1 output is undefined when the mcu accesses the space where its dsi bit is set to 0. 8.1.3.2 multiplexed bus with the multiplexed bus format, the mcu performs data input/output and address output using the same bus by time-sharing. d0 to d7 are time -multiplexed with a0 to a7 in th e space accessed by the 8-bit data bus. d0 to d15 are time-multiplexed with a0 to a15 in the space accessed by the 16-bit data bus. table 8.2 lists multiplexed bus settings and chip-select areas. table 8.3 lists a processor mode and pin function. table 8.2 multiplexed bus settings and chip-select areas note: 1. in microprocessor mode, do not set bits pm05 and pm04 in the pm0 register to 11b. pm05 and pm04 bits setting (1) pm11 and pm10 bits setting 00b (external space mode 0 01b (external space mode 1) 10b (external space mode 2) 11b (external space mode 3) 00b (multiplexed bus not used) separate bus 01b (access the cs2 area using multiplexed bus) do not set to these values cs2 do not set to this value cs2 10b (access the cs1 area using multiplexed bus) cs1 cs1 cs1 m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 51 of 352 rej09b0385-0100 table 8.3 processor mode and pin function notes: 1. do not set bits pm05 and pm04 in the pm0 register to 11b in microprocessor mode since the mcu starts up with the separate bus after reset. 2. these pins are used as address bus when selecting separate bus. 3. bits pm15 and pm14 in the pm1 register determine which pin is used to output the ale signal. 4. the pm02 bit in the pm0 register selects either ?rd , wrl , wrh ? or ?rd , bhe , wr ? combination. 5. p5_6 outputs undefined value when bits pm15 and pm14 are set to 00b (no ale). in this case, it cannot be used as an i/o port. 6. bits pm11 and pm10 in the pm1 register determine wh ether these pins are used as chip-select outputs or address bus. 7. use bits cm01 and cm00 in the cm0 register, bits pm15 and pm14 in the pm1 register, and the pm07 bit in the pm0 register to select among clkout, bclk, and ale function. processor mode microprocessor mode pm05 and pm04 bits setting (1) 00b (multiplexed bus not used) 01b (access cs2 area using multiplexed bus) 10b (access cs1 area using multiplexed bus) data bus width access all external spaces with 8-bit data bus access any external spaces with 16-bit data bus access all external spaces with 8-bit data bus access any external spaces with 16-bit data bus p0_0 to p0_7 data bus (d0 to d7) p1_0 to p1_7 i/o port data bus (d8 to d15) i/o port data bus (d8 to d15) p2_0 to p2_7 address bus (a0 to a7) address bus/data bus (a0/d0 to a7/d7) (2) p3_0 to p3_7 address bus (a8 to a15) address bus/data bus (a8/d8 to a15/d15) (2) p4_0 to p4_3 address bus (a16 to a19) p4_4 to p4_6 cs or address bus (a20 to a22) (refer to 8.2 bus control for details) (6) p4_7 cs or address bus (a23 ) (refer to 8.2 bus control for details) (6) p5_0 to p5_2 rd , wrl , wrh outputs or rd , bhe , wr outputs (refer to 8.2 bus control for details) (4) p5_3 clkout/bclk/ale (7) p5_4 hlda /ale (3) p5_5 hold p5_6 ale (3)(5) p5_7 rdy m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 52 of 352 rej09b0385-0100 8.2 bus control described below are the signals required to access external devices. the si gnals are available in microprocessor mode only. 8.2.1 address bus and data bus address bus is the signals to access 16-mbyte space, an d consists of 24 control pins; a0 to a22 and a23 . a23 is an inverse output signal of the highest-order address bit. data bus is the signals for data input and output. the ds register selects either an 8-bit data bus width from d0 to d7 or a 16-bit data bus width from d0 to d15 for ea ch external space. when a high-level (?h?) signal is applied to the byte pin, the da ta bus accessing the external space 3 is 8 bits wide after reset. when a low-level (?l?) signal is applied to the byte pi n, the data bus accessing the external space 3 is 16 bits wide. 8.2.2 chip-select output chip-select outputs share pins with address bus, a20 to a22 and a23 . bits pm11 and pm10 in the pm1 register determine the cs areas to be accessed and the number of chip-s elect outputs. maximum of four chip-select outputs are provided. in microprocessor mode, no ch ip-select signal is output after reset. only a23 , however, can perform as a chip- select output. the csi pin (i=0 to 3) outputs an ?l? si gnal while accessing its corresponding external space. an ?h? signal is output while the mcu is accessing other external spaces. figure 8.2 shows an ex ample of address bus and chip-select outputs (separate bus). m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 53 of 352 rej09b0385-0100 figure 8.2 address bus and chip-select outputs (separate bus) i = 0 to 3 j = 0 to 3, excluding i k = 0 to 3 p = 0 to 3, excluding k cs1 outputs an "l" signal while accessing the external space 0. cs2 outputs an "l" signal while accessing the external space 1. cs3 outputs an "l" signal while accessing the external space 2. cs0 outputs an "l" signal while accessing the external space 3. note: 1. the above examples show t he address bus and chip-select output in two consecutive bus cycles. depending on t he combination, the chip-select signal c an be more than two bus cycles. when the mcu accesses the space i specified by the same chip-select output in the next cycle after having accessed the external space i, the address bus changes but the chip-select output does not. when the mcu does not access any spaces in the next cycle after having a ccessed an external space (no instruction prefetch is performed), neither address bus nor chip-select signal changes. access the same external space i access external space i data bus address bus chip-select: csk data address data access external space data bus address bus chip-select: csk data address no accesss to external space example 3: after accessing the external space, the address bus changes but the chip-select output does not. example 4: after accessing an external space, neither address bus nor chip-select signal changes. when the mcu accesses the external space j specified by another chip-select output in the next cycle after having accessed the external space i, both address bus and chip-select output change. when the mcu accesses sfr or internal ram area in the next cycle after having accessed an external space, the chip-select signal changes but the address bus does not. access another external space j access external space i data bus address bus chip-select: csk chip-select: csp data address data access external space data bus address bus chip-select: csk data address access sfr, internal ram example 1: after accessing the external space, both address bus and chip-select output change example 2: after accessing an externa l space, the chip-select output changes but the address bus does not. m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 54 of 352 rej09b0385-0100 8.2.3 read/write output signals when using a 16-bit data bus, the pm02 bit in the pm0 register selects either a combination of the ?rd , wr , and bhe ? outputs or the ?rd , wrl , and wrh ? outputs to determine the read/w rite output signals. when the ds3 to ds0 in the ds register are set to 0 (8-bit external data bus width), set the pm02 bit to 0 (rd /wr /bhe ). when any of the ds3 to ds0 bits are set to 1 (16-bit external data bus width) to access an 8-bit space, the combination of ?rd , wr , and bhe ? is automatically selected regardless of the pm02 bit setting. table 8.4 lists rd , wrl , and wrh outputs. table 8.5 list rd , wr , and bhe outputs. the rd , wr , and bhe outputs are selected for the read/write out put signals after reset. when changing to ?rd , wrl , and wrh ? outputs, set the pm02 bit first to write data to an external memory. table 8.4 rd , wrl , and wrh outputs note: 1. these become wr output. table 8.5 rd , wr , and bhe outputs data bus width rd wrl wrh a0 cpu processing on external space 16 bits l h h not used read data h l h not used write 1-byte data to even address h h l not used write 1-byte data to odd address h l l not used write data to both even and odd addresses 8 bits h l (1) not used h/l write 1-byte data lh (1) not used h/l read 1-byte data data bus width rd wr bhe a0 cpu processing on external space 16 bits h l l h write 1-byte data to odd address l h l h read 1-byte data from odd address h l h l write 1-byte data to even address l h h l read 1-byte data from even address h l l l write data to both even and odd addresses l h l l read data from both even and odd addresses 8 bits h l not used h/l write 1-byte data l h not used h/l read 1-byte data m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 55 of 352 rej09b0385-0100 8.2.4 bus timing software wait states for the intern al ram can be set using the pm12 bit in the pm1 register, for the sfr area using the pm13 bit, and for external spaces using the ewcri register (i = 0 to 3). table 8.6 lists a software wait state and bus cycle. the basic bus cycle for the internal ram and sfr area is one bus clock (bclk) cycle. a read or write to the internal ram takes the basic bus cycle. when the pm12 b it in the pm1 register to 1 (1 wait state), an access to the internal ram takes two bclk cycles. a read or write to the sfr area takes two bclk cycles (1 wait state). when the pm13 bit in the pm1 register is set to 1 (2 wait states), an access takes three bclk cycles. the external bus cycle is divided into two phases: the number of bclk cycles in the period from the beginning of the bus access until the read or writ e output signal b ecomes ?l? (first ), and the number of bclk cycles in the period from the read or write output signal becomes ?l? until the signal changes to ?h? (second ). the minimum read or write cycle for the ex ternal bus is two bcl k clock cycles (1 + 1 ). the ewcri register (i = 0 to 3) selects an ex ternal bus cycle from 12 types for the separate bus and seven types for the multiplexed bus. for example, when bits ewcri4 to ewcri0 in the ewcri register are set to 00011b (1 +3 ), the external bus cycle is four bclk cycles. figure 8.3 shows the ewcri register. figures 8.4 to 8.8 show external bus timings. figure 8.3 ewcr0 to ewcr3 registers b7 b6 b5 b4 b1 b2 b3 external space wait contro l register i (i = 0 to 3) symbol ewcr0 to ewcr3 address 0048h, 0049h, 004ah, 004bh bit symbol bit name rw ewcri0 after reset x0x0 0011b rw b0 function ewcri1 rw rw ewcri2 ewcri3 ewcri4 ? (b5) ? (b7) rw rw ? bus cycle select bits (3) b4 b3 b2 b1 b0 (1) (2) 0 0 0 0 1: 1 + 1 0 0 0 1 0: 1 + 2 0 0 0 1 1: 1 + 3 0 0 1 0 0: 1 + 4 0 0 1 0 1: 1 + 5 0 0 1 1 0: 1 + 6 0 1 0 1 0: 2 + 2 0 1 0 1 1: 2 + 3 0 1 1 0 0: 2 + 4 0 1 1 0 1: 2 + 5 1 0 0 1 1: 3 + 3 1 0 1 0 0: 3 + 4 1 0 1 0 1: 3 + 5 1 0 1 1 0: 3 + 6 do not set to values other than the above unimplemented. write 0. read as undefined value. unimplemented. write 0. read as undefined value. recovery cycle insert select bit 0: insert no recovery cycle when accessing external space i 1: insert a recovery cycle when accessing external space i ewcri6 rw ? notes: 1. the number of bclk cycles in the period from the beginning of the bus access until the read or write output signal beco mes "l". 2. the number of bclk cycles in the period from the read or write output signal becomes "l" until the signal changes to "h ". m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 56 of 352 rej09b0385-0100 table 8.6 software wait state and bus cycle space external bus status pm1 register ewcri register (i=0 to 3) bus cycle pm13 bit pm12 bit ewcri4 to ewcri0 bits sfr area ? 0 ?? 2 bclk cycles 1 3 bclk cycles internal ram ?? 0 ? 1 bclk cycle 1 2 bclk cycles external memory separate bus ?? 00001b 2 bclk cycles 00010b 3 bclk cycles 00011b 4 bclk cycles 00100b 5 bclk cycles 00101b 6 bclk cycles 00110b 7 bclk cycles 01010b 4 bclk cycles 01011b 5 bclk cycles 01100b 6 bclk cycles 10011b 6 bclk cycles 10100b 7 bclk cycles 10110b 9 bclk cycles multiplexed bus ?? 01010b 4 bclk cycles 01011b 5 bclk cycles 01101b 7 bclk cycles 10011b 6 bclk cycles 10100b 7 bclk cycles 10101b 8 bclk cycles 10110b 9 bclk cycles m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 57 of 352 rej09b0385-0100 figure 8.4 bus cycles when separate bus is selected (1) ? bus cycle 1 + 1 bclk address csi read data write data rd wr, wrl, wrh ? bus cycle 1 + 2 ? bus cycle 1 + 3 bclk address csi read data write data rd wr , wrl , wrh ? bus cycle 1 + 4 bclk address csi read data write data rd wr , wrl , wrh ? bus cycle 1 + 5 bclk address csi read data write data rd wr , wrl , wrh bclk address csi read data write data rd wr, wrl, wrh ? bus cycle 1 + 6 bclk address csi read data write data rd wr , wrl , wrh 1 bus cycle = 3 1 bus cycle = 5 1 bus cycle = 4 1 bus cycle = 6 (1) (1) (1) (1) (1) i = 0 to 3 1 bus cycle = 2 1 bus cycle = 7 (1) note: 1. when the mcu accesses the same cs area consecutively, the csi pin keeps outputting "l". m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 58 of 352 rej09b0385-0100 figure 8.5 bus cycles when separate bus is selected (2) ? bus cycle 2 + 2 bclk address csi read data write data rd wr, wrl, wrh ? bus cycle 2 + 3 ? bus cycle 2 + 4 bclk address csi read data write data rd wr, wrl, wrh bclk address csi read data write data rd wr, wrl, wrh (1) (1) (1) 1 bus cycle = 5 1 bus cycle = 6 1 bus cycle = 4 note: 1. when the mcu accesses the same cs area consecutively, the csi pin keeps outputting "l". i = 0 to 3 m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 59 of 352 rej09b0385-0100 figure 8.6 bus cycle with separate bus is selected(3) ? bus cycle 3 + 3 ? bus cycle 3 + 6 bclk address csi read data write data rd wr, wrl, wrh ? bus cycle 3 + 4 bclk address csi read data write data rd wr, wrl, wrh bclk address csi read data write data rd wr , wrl , wrh (1) (1) (1) 1 bus cycle = 6 1 bus cycle = 7 1 bus cycle = 9 note: 1. when the mcu accesses the same cs area consecutively, the csi pin keeps outputting "l". i = 0 to 3 m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 60 of 352 rej09b0385-0100 figure 8.7 bus cycles when multiplexed bus is selected (1) 1 bus cycle = 6 1 bus cycle = 7 rd rd ? bus cycle 2 + 2 bclk csi read data write data rd ? bus cycle 2 + 3 ? bus cycle 2 + 5 ale bclk csi read data write data rd ale bclk csi read data write data rd ale (1) (1) (1) ? bus cycle 3 + 3 bclk csi read data write data rd ale (1) la la 1 bus cycle = 4 wd la la wd la la i=0 to 3 la la rd wd rd wd wr (wrl) wr (wrl) wr (wrl) wr (wrl) 1 bus cycle = 5 la: latch address rd: read data wd: write data note: 1. when the mcu accesses the same cs area consecutively, the csi pin keeps outputting "l". m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 61 of 352 rej09b0385-0100 figure 8.8 bus cycles when multiplexed bus is selected (2) rd rd rd la: latch address rd: read data wd: write data ? bus cycle 3 + 6 bclk csi read data write data rd wr (wrl) ale (1) ? bus cycle 3 + 5 bclk csi read data write data rd wr (wrl) ale (1) ? bus cycle 3 + 4 bclk csi read data write data rd wr (wrl) ale (1) wd 1 bus cycle = 7 la la wd 1 bus cycle = 8 la la wd 1 bus cycle = 9 la la i = 0 to 3 note: 1. when the mcu accesses the same cs area consecutively, the csi pin keeps outputting "l". m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 62 of 352 rej09b0385-0100 8.2.4.1 bus cycle with recovery cycle inserted the ewcri6 bit in the ewcri register (i = 0 to 3) determines whether the recovery cycle is inserted or not. address output or data output is held during the recovery cycle (only when using the separate bus). devices, which require longer address hold time or data hold time, are connectable. figure 8.9 recovery cycle rd rd - recovery cycle when separate bus is selected ( bus cycle is 1 + 2 ) bclk address csi read data write data rd wr, wrl, wrh - recovery cycle when multiplexed bus is selected ( bus cycle is 2 + 3 ) a: address la: latch address rd: read data wd: write d ata i = 0 to 3 note: 1. when the mcu accesses the same cs area consecutively, t he csi pin keeps outputting "l". (1) recovery cycle address is held wd a bclk csi read data write data rd wr (wrl) ale (1) wd la la recovery cycle data is held data is held m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 63 of 352 rej09b0385-0100 8.2.5 ale output the ale output signal is provided for the external devices to latch the address when using the multiplexed bus. latch the address at the falling edge of the ale output. bits pm15 and pm14 in the pm1 register determine to what pin the ale output is assigned. the ale signal is output even when accessing the internal space. figure 8.10 ale output and address/data bus 8.2.6 rdy input the rdy signal facilitates access to external devi ces requiring longer access time. when rdy input is ?l? at the falling edge of the last bclk cycle, wait states are in serted into the bus cycle. then, when an ?h? signal is input to the rdy pin at the falling edge of bclk, the mcu resumes executing the remaining bus clock. table 8.7 lists mcu states when placed in wait state by rdy input. figure 8.11 shows an example of the rd signal that is extended by the rdy signal. table 8.7 mcu states while ?l? is input to the rdy pin item state clock generation circui ts operating (oscillating) rd , wr , a0 to a22, a23 , d0 to d15, cs0 to cs3 , ale, hlda , programmable i/o ports maintains the same state as when ?l? is input to rdy pin. internal peripheral circuits operating (1) 8-bit data bus ale d0/a0 to d7/a7 note: 1. d0/a0 to d15/a15 are placed in high-impedance states wh en read. address data (1) address address address or cs a8 to a15 a16 to a19 a20/cs3 a21/cs2 a22/cs1 a23/cs0 ale d0/a0 to d15/a15 address data (1) address address or cs a16 to a19 (2) 16-bit data bus a20/cs3 a21/cs2 a22/cs1 a23/cs0 m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 64 of 352 rej09b0385-0100 figure 8.11 rd output signal extended by rdy input 8.2.7 hold input the hold input signal is used to transfer ownership of the bus from the cpu to external devices. when a low- level (?l?) signal is applied to the hold pin, the mcu enters a hold state after the bus access in progress is completed. while the hold pin is held ?l?, the mcu remains in a hold state and the hlda pin outputs an ?l? signal. table 8.8 lists th e mcu states in hold state. bus is used in the following priority order: hold , dmac, cpu. table 8.8 mcu states in hold state note: 1. when the pm22 bit in the pm2 register is set to 1 (selec ts the on-chip oscillator clock as count source for the watchdog timer), watchdog timer does not stop. item state clock generation circuits operating (oscillating) cpu stopped internal peripheral circuits operating (watchdog timer is stopped) (1) rd , wr , a0 to a22, a23 , d0 to d15, cs0 to cs3 , bhe high-impedance hlda outputs ?l? ale outputs ?l? programmable i/o ports maintains the same state as when ?l? is input to hold pin. - separate bus (bus cycle is 1 + 2 ) bclk rd csi (1) rdy timing to input rdy signal - multiplexed bus (bus cycle is 1 + 2 ) bclk rd csi (1) rdy tsu(rdy-bclk) timing to input rdy signal note: 1. chip-select output (csi) may be extended depending on t he cpu state such as the instruction queue buffer. tsu(rdy-bclk): rdy input setup time : wait states inserted by rdy input i = 0 to 3 tsu(rdy-bclk) m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 65 of 352 rej09b0385-0100 8.2.8 external bus states wh en accessing internal space table 8.9 lists external bus states when the internal space is accessed. table 8.9 external bus states when accessing internal space 8.2.9 bclk output the bus clock can be output from the bclk pin in micr oprocessor mode. to output the bus clock, set the pm07 bit in the pm0 register to 0 (bclk output) and bits cm01 and cm00 in the cm0 register to 00b (i/o port p5_3). refer to 9. clock genera tion circuits for details . item state when accessing sfr and internal ram a0 to a22, a23 hold the last accessed address in the external space d0 to d15 high-impedance rd , wr , wrl , wrh outputs ?h? bhe holds the output level at the time when the mcu accessed the external space or sfr area for the last time cs outputs ?h? ale outputs ale signal m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 66 of 352 rej09b0385-0100 8.3 page mode control function the page mode control function allows high-speed read access to the external memory compatible with the page mode control. while the mcu accesses data within the ei ght-byte block of consecutive addresses which have the same 21 high-order bits, less cycl es are required for the subsequent bus accesses than the first bus access. the ewcri register (i = 0 to 3) determines how many wait states are inserted for the first bus access. registers pwcr0 and pwcr1 determine how many wait states are in serted for the subsequent bus accesses. use the following procedure to enable the page mode control. (1) set bits ewcri4 to ewcri 0 in the ewcri register. (2) set bits pwcrj02 to pwcrj00 and bits pwcrj06 to pwcrj04 in the pwcrj register (j = 0, 1). (3) set bits pwcrj03 and pwcrj07 to 1 (page mode control enabled). when using the page mode control function, access all the external spaces using page m ode control. it is not allowed to combine the page mode controlled access and the nor mal access to external spaces. set bits pm05 and pm04 to 00b (multiplexed bus is not us ed). the page mode control function and multiplexed bus cannot be used at the same time. figure 8.12 and 8.13 show registers pwcr0 and pwcr1. figure 8.14 shows a diagram of external bus timing with page mode function. figure 8.12 pwcr0 register b7 b6 b5 b4 b1 b2 b3 page mode wait control register 0 bit symbol bit name rw pwcr000 note: 1. when page mode control is enabled, set the ewcri6 bit i n the ewcri register (i = 0 to 3) to 0 (add no recovery cycle when accessing external space i ). b0 function external space 0 subsequent access wait select bits pwcr001 pwcr002 b2 b1 b0 0 0 1: 1 + 1 0 1 0: 1 + 2 0 1 1: 1 + 3 1 0 0: 1 + 4 do not set to values other than the above. pwcr003 pwcr005 rw pwcr004 pwcr006 pwcr007 external space 0 page mode control enable bit 0: page mode control disabled 1: page mode control enabled (1) external space 1 subsequent access wait select bits b6 b5 b4 0 0 1: 1 + 1 0 1 0: 1 + 2 0 1 1: 1 + 3 1 0 0: 1 + 4 do not set to values other than the above. external space 1 page mode control enable bit 0: page mode control disabled 1: page mode control enabled (1) rw rw rw rw rw rw rw symbol pwcr0 address 004ch after reset 0001 0001b m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 67 of 352 rej09b0385-0100 figure 8.13 pwcr1 register symbol pwcr1 address 004dh after reset 0001 0001b b7 b6 b5 b4 b1 b2 b3 page mode wait control register 1 bit symbol bit name rw pwcr100 note: 1. when page mode control is enabled, set the ewcri6 bit i n the ewcri register (i = 0 to 3) to 0 (add no recovery cycle when accessing external space i ). b0 function external space 2 subsequent access wait select bits pwcr101 pwcr102 b2 b1 b0 0 0 1: 1 + 1 0 1 0: 1 + 2 0 1 1: 1 + 3 1 0 0: 1 + 4 do not set to values other than the above. pwcr103 pwcr105 rw pwcr104 pwcr106 pwcr107 external space 2 page mode control enable bit 0: page mode control disabled 1: page mode control enabled (1) external space 3 subsequent access wait select bits b6 b5 b4 0 0 1: 1 + 1 0 1 0: 1 + 2 0 1 1: 1 + 3 1 0 0: 1 + 4 do not set to values other than the above. external space 3 page mode control enable bit 0: page mode control disabled 1: page mode control enabled (1) rw rw rw rw rw rw rw m32c/8a group 8. bus rev.1.00 jul 15, 2007 page 68 of 352 rej09b0385-0100 figure 8.14 external bus timing with page mode control function fff00ch fff008h fff001h fff000h 3 + 3 cs0 (ce) 1 + 2 bclk address data rd (oe) fff002h 1 + 2 fff007h 1 + 2 fff008h 3 + 3 fff009h 1 + 2 if the mcu accesses data in other than the eight-b yte block of consecutive addres ses, the page mode controlled access is started over from the first bus access. set using bits pwcr106 to pwcr104 set using bits ewcr34 to ewcr30 the above applies under the following conditions: - bits pm11 and pm10 in the pm1 register are set to 11b (mode 3 ). - the ds3 bit in the ds regiter is set to 0 (8 bits wide). - bits ewcr34 to ewcr30 in the ewcr3 register are set to 10011b (3 + 3 ). - the ewcr36 bit is set to 0 (add no recovery cycle when access ing external space 3). - bits pwcr106 to pwcr104 are set to 010b (1 + 2 ). - the pwcr107 bit is set to 1 (page mode control enabled). fff002h fff000h 3 + 3 cs0 (ce) 1 + 2 bclk address data rd (oe) fff004h 1 + 2 fff006h 3 + 3 fff00ah 1 + 2 the above applies under the following conditions: - bits pm11 and pm10 in the pm1 register are set to 11b (mode 3 ). - the ds3 bit in the ds regiter is set to 1 (16 bits wide). - bits ewcr34 to ewcr30 in the ewcr3 register are set to 10011b (3 + 3 ). - the ewcr36 bit is set to 0 (add no recovery cycle when access ing external space 3). - bits pwcr106 to pwcr104 are set to 010b (1 + 2 ). - the pwcr107 bit is set to 1 (page mode control enabled). 1 + 2 1 + 2 set using bits pwcr106 to pwcr104 set using bits ewcr34 to ewcr30 8-bit data bus width 16-bit data bus width m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 69 of 352 rej09b0385-0100 9. clock generation circuits 9.1 types of the clo ck generation circuit the mcu has four on-chip clock generation circuits to generate system clock signals. ? main clock oscillation circuit ? sub clock oscillation circuit ? on-chip oscillator ? pll frequency synthesizer table 9.1 lists the specifications of the clock generation ci rcuit. figure 9.1 shows a block diagram of the clock generation circuit. figures 9.2 to 9.8 show clock-associated registers. table 9.1 clock generation circuit specifications item main clock oscillation circuit sub clock oscillation circuit on-chip oscillator pll frequency synthesizer applications ? cpu clock source ? peripheral function clock source ? cpu clock source ? count source for timer a and timer b ? cpu clock source ? peripheral function clock source ? cpu clock source ? peripheral function clock source clock frequency up to 32 mhz 32.768 khz approx. 1 mhz up to 32 mhz (see table 9.3 ) connectable oscillator or resonator ? ceramic resonator ? crystal oscillator crystal oscillator ?? oscillator or resonator connect pins xin, xout xc in, xcout ?? oscillation stop/ restart function available available available available oscillator state after reset oscillating stopped stopped stopped other externally generated clock can be used. externally generated clock can be used. oscillation stop detect function: when the main clock stops, the on-chip oscillator starts oscillating automatically and becomes the cpu and peripheral function clock source 30 mhz or 20 mhz: input 10 mhz to the main clock 32 mhz or 21.3 mhz input 8 mhz to the main clock m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 70 of 352 rej09b0385-0100 figure 9.1 clock generation circuit wait instruction s r q pll frequency synthesizer on-chip oscillator enable oscillation cm17 cm21 divider (divide-by-m) cm04 xcin xcout sub clock oscillation circuit xin xout main clock oscillation circuit 1/8 1/4 froc 1/2n fad f1 f8 f32 f2n (1) pm27 pm26 cst peripheral function clock source: fpfc fxind froc 1/32 fc32 cpsr=1 cpu clock (bus clock) fcpu cm05 pm26 fxind vc27 cm07 stop mode pm26 pm27 pm22 cm21 stop mode cm02 pm21 clock stop signal in wait mode clock stop signal in wait mode stop mode software reset watchdog timer reset hardware reset 2 reset the divider (divide- by-8 mode) main clock clock stop signal in wait mode cm05 cm21 cm10 clock stop signal in wait mode stop mode interrupt request level determination output reset vdet4 detection interrupt signal nmi s q r logic 1 write signal to cm10 bit reset the divider fc fpll 0 1 0 1 0 1 00 01 10 vc27: bit in the vcr2 register cm02, cm04, cm05, and cm07: bits in the cm0 register cm10 and cm17: bits in the cm1 register cm21: bit in the cm2 regsiter pm21, pm22, pm26, and pm27: bits in the pm2 register cst: bit in the tcspr register cpsr: bit in the cpsrf register notes: 1. bits cnt3 to cnt0 in the tcspr register select no divis ion (n = 0) or divide-by-2n (n = 1 to 15). 2. bits mcd4 to mcd0 in the mcd register select the dividi ng ratio (divide-by-m mode: m = 1, 2, 3, 4, 6, 8, 10, 12, 14, 1 6). programmable counter reference frequency counter phase comparator 1/2 pll clock (fpll) plc12: bit in the plc1 register vco clock (fvco) pll frequency synthesizer charge pump voltage controlled oscillator (vco) plc12 1/3 watchdog timer interrupt request signal oscillation stop detection interrupt request (non-maskable interrupt requst) cm21 vdet4 detection interrupt request signal oscillation stop detection circuit clock edge detect/ charge and discharge circuit control main clock charge and discharge circuit oscillation stop detection interrupt request generation circuit main clock mcd register (2) m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 71 of 352 rej09b0385-0100 figure 9.2 cm0 register b7 b6 b5 b4 b1 b2 b3 system clock control register 0 (1) symbol cm0 address 0006h bit symbol bit name rw cm00 after reset 0000 1000b rw notes: 1. set the cm0 register after the prc0 bi t in the prcr register is set to 1 (write enable). 2. the bclk, ale, or "l" signal is output from the p 5_3 pin in microprocessor mode. the p5_3 does not function as an i/o p ort. 3. fc32 does not stop running. 4. to set the cm04 bit to 1, set bits pd8_7 and pd8_6 in the pd8 register to 00b (ports p8_6 and p8_7 in input mode) and t he pu25 bit in the pur2 register to 0 (no pull-up). 5. the cm05 bit stops the main clock oscillation when ent ering low-power consumption mode or on-chip oscillator low-power consumption mode. the cm05 bit cannot be us ed to determine whether the main clock stops or not. to stop the main clock oscillation, set the plc07 bit in the plc0 register to 0 and t he cm05 bit to 1 after setting the cm07 bit to 1 or setting the c m21 bit in the cm2 register to 1 (on-chip oscillator clock). when the cm05 bit is set to 1, the xout pin outputs "h". since an on-chip feedback resistor remains on, the xin pin i s pulled up to the xout pin via the feedback resistor. 6. when the cm05 bit is set to 1, bits mcd4 to mcd0 in the mcd register become 01000b (divide-by-8 mode). in on-chip oscillator mode, bits mcd4 to mcd0 do not become 01000b even if the cm05 bit is set to 1. 7. once the cm06 bit is set to 1, it cannot be set to 0 by program. 8. change the cm07 bit setting from 0 to 1, after t he cm04 bit is set to 1 and the sub clock oscillation stabilizes. change the cm07 bit setting from 1 to 0, after the cm05 bit is set to 0 and the main clock osc illation stabilizes. do not change the cm07 bit simultaneously with the cm04 or cm05 bit. 9. if the pm21 bit in the pm2 register is set to 1 (d isables a clock change), a write to bits cm02, cm05, and cm07 has no effect. 10. when stop mode is entered, the cm03 bit becomes 1. b0 function b1 b0 0 0: i/o port p5_3 (2) 0 1: outputs fc 1 0: outputs f8 1 1: outputs f32 clock output function select bits (2) cm01 cm02 peripheral function clock stop in wait mode bit (9) 0: peripheral clocks do not stop in wait mode 1: peripheral clocks stop in wait mode (3) cm03 xcin-xcout drive capability select bit (10) 0: low 1: high cm04 port xc switch bit 0: i/o port function 1: xcin-xcout oscillation function (4) cm05 main clock (xin-xout) stop bit (5, 9) 0: main clock oscillates 1: main clock stops (6) cm06 watchdog timer function select bit cpu clock select bit 0 (8, 9) 0: watchdog timer interrupt 1: reset (7) cm07 0: clock selected by the cm21 bit divided by the mcd register 1: sub clock rw rw rw rw rw rw rw m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 72 of 352 rej09b0385-0100 figure 9.3 cm1 register b7 0 0 0 0 1 0 b6 b5 b4 b1 b2 b3 system clock control register 1 (1) symbol cm1 address 0007h bit symbol bit name rw cm10 after reset 0010 0000b notes: 1. set the cm1 register after the prc0 bi t in the prcr register is set to 1 (write enable). 2. when the cm10 bit is set to 1, the xout pin output s "h" and the built-in feedback resistor is disconnected. pins xin, xcin, and xcout are placed in high-impedance states. 3. when the cm10 bit is set to 1, bits mcd4 to mcd0 in the mcd register become 01000b (divide-by-8 mode). do not set the cm10 bit to 1, when the cm20 bit in the cm2 register is set to 1 (oscillation stop detect function enab led) or the cm21 bit in the cm2 register is set to 1 (on-chip o scillator clock selected). 4. set the cm17 bit to 1 after the pll clock oscillation stablilizes. 5. if the pm21 bit in the pm2 register is set to 1 (disables a clock change), writes to bits cm10 and cm17 have no effect. if the pm22 bit in the pm2 register is set to 1 (on-chip oscillator clock as watchdog timer count source), a write to the cm10 bit has no effect. b0 function all clock stop control bit (2, 3, 5) ? (b4-b1) ? (b5) reserved bits 0: clock oscillates 1: all clocks stop (stop mode) ? (b6) set to 0 cm17 cpu clock select bit 1 (4, 5) set to 1 0: main clock 1: pll clock rw set to 0 reserved bit reserved bit rw rw rw rw m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 73 of 352 rej09b0385-0100 figure 9.4 mcd register b7 b6 b5 b4 b1 b2 b3 main clock division register (1) symbol mcd address 000ch bit symbol bit name rw mcd0 after reset xxx0 1000b notes: 1. set the mcd register after the prc0 bit in the prcr register is set to 1 (write enable). 2. when stop mode or low-power consumption mode is entered, bits mcd4 to mcd0 become 01000b. in on-chip oscillator mode, bits mcd4 to mcd0 do not become 01000b even if the cm05 bit in the cm0 register is set to 1 (main clock stops). b0 function main clock division select bits (2) mcd1 mcd2 b4 b3 b2 b1 b0 1 0 0 1 0: divide-by-1 (no division) mode 0 0 0 1 0: divide-by-2 mode 0 0 0 1 1: divide-by-3 mode 0 0 1 0 0: divide-by-4 mode 0 0 1 1 0: divide-by-6 mode 0 1 0 0 0: divide-by-8 mode 0 1 0 1 0: divide-by-10 mode 0 1 1 0 0: divide-by-12 mode 0 1 1 1 0: divide-by-14 mode 0 0 0 0 0: divide-by-16 mode do not set to values other than the above mcd3 mcd4 rw rw rw rw rw ? (b7-b5) ? reserved bits read as undefined value m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 74 of 352 rej09b0385-0100 figure 9.5 cm2 register b7 0 0 0 0 b6 b5 b4 b1 b2 b3 oscillation stop detection register (1) symbol cm2 address 000dh bit symbol bit name rw cm20 after reset 00h notes: 1. set the cm2 register after the prc0 bi t in the prcr register is set to 1 (write enable). 2. if the pm21 bit in the pm2 register is set to 1 (disables a clock change), a write to the cm20 bit has no effect. 3. when a loss of the main clock is detected while the cm20 bit is set to 1, the cm21 bit becomes 1. although the main clock restarts oscillating, the cm 21 bit does not become 0. to use t he main clock as the cpu clock s ource after the main clock restarts oscillati ng, set the cm21 bit to 0 by program. 4. when both the cm20 and cm22 bits are set to 1, do not set the cm21 bit to 0. 5. when a loss of the main clock is detected, the cm22 bi t becomes 1. the cm22 bit can only be set to 0, not 1, by program . if the cm22 bit is set to 0 by program while t he main clock is stopped, the cm22 bit does not become 1 until another l oss of the main clock is detected after the main clock restarts oscillating. 6. determine the main clock state by reading the cm23 bit several times after the oscillation stop detection interrupt is generated. b0 function oscillation stop detection enable bit (2) cm21 cm22 cpu clock select bit 2 (3, 4) 0: oscillation stop det ect function not used 1: oscillation stop detect function used cm23 ? (b7-b4) reserved bits set to 0 rw oscillation stop detection flag (5) main clock monitor flag (6) ro rw rw rw 0: clock selected by the cm17 bit 1: on-chip oscillator clock 0: loss of main clock not detected 1: loss of main clock detected 0: main clock oscillates 1: main clock stops m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 75 of 352 rej09b0385-0100 figure 9.6 plc0 register, plc1 register b7 1 0 1 b6 b5 b4 b1 b2 b3 pll control register 0 (1, 2, 5) symbol plc0 address 0026h bit symbol bit name rw plc00 after reset 0001 x010b notes: 1. set the plc0 register after the prc0 bit in the prcr register is set to 1 (write enable). 2. if the pm21 bit in the pm2 register is set to 1 (disables a clock chang), a write to the plc0 register has no effect. 3. set bits plc02 to plc00 while the plc07 bit is 0. bits plc02 to plc00 can be written only once. 4. enter wait mode or stop mode after the cm17 bit is set to 0 (main clock as cpu clock source) and then the plc07 bit to 0. 5. set registers plc0 and plc1 simultaneously in 16-bit units . b0 function programmable counter select bits (3) plc01 plc02 the vco clock is the main clock multiplied by the following variables. b2 b1 b0 0 1 1: multiply-by-6 1 0 0: multiply-by-8 do not set to values other than the above ? (b3) ? (b4) rw rw rw ? (b5) rw reserved bit set to 1 set to 1 ? (b6) plc07 reserved bit reserved bit set to 0 0: pll stops 1: pll runs operation enable bit (4) ? rw rw rw notes: 1. set the plc1 register after the prc0 bi t in the prcr register is set to 1 (write enable). 2. if the pm21 bit in the pm2 register is set to 1 (disables a clock change), a write to the the plc1 register has no effe ct. 3. set the plc1 register while the plc07 bit is 0 (pll stopped).the plc1 register can be written only once. 4. set registers plc0 and plc1 simultaneously in 16-bit units. read as undefined value reserved bit b7 b6 b5 b4 b1 b2 b3 pll control register 1 (1, 2, 3, 4) bit symbol bit name rw ? (b0) rw b0 function reserved bit ? (b1) rw reserved bit 0 0 0 0 1 0 plc12 rw 0: divide-by-2 1: divide-by-3 pll clock division select bit ? (b3) rw reserved bit ? (b4) ? read as undefined value reserved bit ? (b7-b5) rw reserved bits set to 0 set to 1 set to 0 set to 0 syambol plc1 address 0027h after reset 000x 0000b m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 76 of 352 rej09b0385-0100 figure 9.7 pm2 register b7 b6 b5 b4 b1 b2 b3 processor mode register 2 (1) symbol pm2 address 0013h bit symbol bit name rw ? (b0) after reset 00h rw notes: 1. set the pm2 register after the prc1 bit in the prcr register is set to 1 (write enable). 2. once bits pm22 and pm21 are set to 1, they cannot be set to 0 by program. 3. when the pm21 bit is set to 1, ? the cpu clock does not stop, even if the wait instruction is executed; ? writes to the following bits have no effect. - the cm02 bit in the cm0 register - the cm05 bit in the cm0 register - the cm07 bit in the cm0 register (cpu clock source is not changed) - the cm10 bit in the cm1 register (the mcu does not enter stop mode) - the cm17 bit in the cm1 register (cpu clock source is not changed) - the cm20 bit in the cm2 r egister (oscillation stop detect function setting is not changed) - all bits in registers plc0 and plc1 (pll frequency synthesizer setting is not changed) 4. when the pm22 bit is set to 1, ? the on-chip oscillator starts oscillating and t he on-chip oscillator clock becomes the count source for the watchdog timer; ? write to the cm10 bit in the cm1 register is disabled (writing a 1 has no effect and the mcu does not enter stop mod e); ? the watchdog timer keeps operating when the mcu is in wait mode or in hold state. b0 function b7 b6 0 0: clock selected by the cm21 bit 0 1: xin clock (fxind) 1 0: on-chip oscillator clock (froc) 1 1: do not set to this value reserved bit pm21 pm22 system clock protect bit (2, 3) 0: protects a clock by the prcr register 1: disables a clock change ? (b5-b3) wdt count source protect bit (2, 4) set to 0 pm26 f2n clock source select bits pm27 rw rw rw rw rw reserved bits set to 0 0 0 0 0 0: cpu clock as count source for the watchdog timer 1: on-chip oscillator clock as count source for the watchdog timer m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 77 of 352 rej09b0385-0100 figure 9.8 tcspr register, cpsrf register b7 b6 b5 b4 b1 b2 b3 count source prescaler register symbol tcspr address 035fh bit symbol bit name rw cnt0 after reset (2) 0xxx 0000b notes: 1. set bits cnt3 to cnt0 after the cst bit is set to 0. 2. the tcspr register maintains values set before reset, even after the software reset or watchdog timer reset has been pe rformed. b0 function division rate select bits (1) cnt1 cnt2 if the setting value is n, f2n is the main clock, on-chip oscillator clock, or pll clock divided by 2n. when n is set to 0, no division is selected cnt3 ? (b6-b4) ? rw rw rw rw cst operation enable bit rw reserved bits read as undefined value 0: divider stops 1: divider operates clock prescaler reset register b7 b6 b5 b4 b1 b2 b3 symbol cpsrf address 0341h bit symbol bit name rw ? (b6-b0) after reset 0xxx xxxxb b0 function unimplemented. write 0. read as undefined value. cpsr rw ? clock prescaler reset bit when the cpsr bit is set to 1, a divider for fc32 is reset. read as 0. m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 78 of 352 rej09b0385-0100 9.1.1 main clock main clock oscillation circuit generates the main clock. the main clock is used as the clock source for the cpu clock and peripheral function clocks. the main clock oscillation circuit is configured by connecting an oscill ator between the xin and xout pins. the circuit has an on-chip feedback re sistor. the feedback resistor is disc onnected from the oscillation circuit in stop mode to reduce power consumption. the main clock oscillation circuit may also be configured by feeding an externally generated clock to the xin pin. figure 9.9 shows examples of main clock circuit connection. circuit constants vary depending on each oscillator. us e the circuit constant recommended by each oscillator manufacturer. the main clock divided-by-eight becomes the cpu clock source after reset. to reduce power consumption, set the cm05 bit in the cm 0 register to 1 (main clock stopped) after the sub clock or on-chip oscillator clock is selected as the cpu clock sources. in this case, the xout pin outputs an ?h? signal. the xin pin is pulled up to the xout pin via the feedback resistor which remains on. when an external clock is input to the xin pin, do not set the cm05 bit to 1. all clocks, including the main clock, stop in stop mode. refer to 9.5 power consumption control for details. figure 9.9 main clock circuit connection xin xout oscillator cin cout rd (1) mcu (on-chip feedback resistor) xin xout mcu (on-chip feedback resistor) open externally generated clock vcc vss vss note: 1. insert a damping resistor if required. resistance values vary depending on the oscilla tor setting. use the resistance values recommended by the oscillator manufacturer. if the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback resistor between xin and xout following the instructions. m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 79 of 352 rej09b0385-0100 9.1.2 sub clock sub clock oscillation circuit generates the sub clock. th e sub clock is used as the clock source for the cpu clock and for timer a and timer b. fc, which has the sa me frequency as the sub clock can be output from the clkout pin. the sub clock oscillation circuit is configured by c onnecting a crystal oscillator between the xcin and xcout pins. the circuit has an on-chip feedback resist or. the feedback resistor is disconnected from the oscillation circuit in stop mode to reduce power consum ption. the sub clock oscillation circuit may also be configured by feeding an externally generated clock to the xcin pin. figure 9.10 shows an example of sub clock circuit connection. circuit constants vary depe nding on each oscillator. use the circuit constant recommended by each osci llator manufacturer. the sub clock is stopped after reset, and the feedback re sistor is disconnected from the oscillation circuit. to start oscillating the sub clock oscillation circuit, set bo th the pd8_7 and pd8_6 bits in the pd8 register to 0 (input mode), the pu25 bit in the pur2 register to 0 (no pull-up), and then the cm04 bit in the cm0 register to 1 (xcin-xcout oscillation function). to input the extern ally generated clock to the xcin pin, set the pd8_7 bit to 0, the pu25 bit to 0, and then the cm04 bit to 1. a clock input to the xcin pin becomes the clock source for the sub clock. when the cm07 bit in the cm0 register is set to 1 (sub clock) after the sub clock oscillation stabilizes, the sub clock becomes the cpu clock source. all clocks, including the sub clock, stop in stop mode. refer to 9.5 power consumption control for details. figure 9.10 sub clock circuit connection xcin xcout oscillator ccin ccout rcd (1) mcu (on-chip feedback resistor) xcin xcout mcu (on-chip feedback resistor) open externally generated clock vcc vss vss note: 1. insert a damping resistor if required. resistance values vary depending on the oscillator setting. use the resistance values recommended by the oscillator manufacturer. if the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback resistor between xcin and xcout following the instructions. m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 80 of 352 rej09b0385-0100 9.1.3 on-chip oscillator clock on-chip oscillator generates the 1-mhz on-chip oscillator clock. the on-chip oscillator clock is used as the clock source for the cpu clock and peripheral function clocks. the on-chip oscillator clock is stoppe d after reset. when the cm21 bit in the cm2 register is set to 1 (on-chip oscillator clock), the on-chip oscillato r starts oscillating and becomes the clock source for the cpu clock and peripheral function clocks in place of the main clock. table 9.2 lists on-chip oscillator start conditions. table 9.2 on-chip osci llator start condition 9.1.3.1 oscillation stop detect function when the main clock is terminated running by an external factor, the on -chip oscillator automatically starts oscillating. when the cm 20 bit in the cm2 register is set to 1 (o scillation stop detect function used), an oscillation stop detection interrupt request is generated as soon as the main clock is lost. simulta neously, the on-chip oscillator starts oscillating. the on- chip oscillator clock takes the place of the main clock as the clock source for the cpu clock and peripheral function clocks. associated bits in the cm2 register are changed as follows: ? cm21 bit becomes 1 (on-chip osci llator clock becomes the cpu clock) ? cm22 bit becomes 1 (loss of main clock stop is detected) ? cm23 bit becomes 1 (main clock stops) the oscillation stop detection interrupt shares the ve ctor with the watchdog timer interrupt and the vdet4 detection interrupt. when these interrupts are used simu ltaneously, verify the cm22 bit within an interrupt routine to determine if an oscillation stop de tection interrupt request has been generated. when the main clock resumes its operation after a loss of the main clock is detected, the main clock can be selected as the clock source for the cpu clock and peripheral function clocks by program. figure 9.11 shows the procedure to switch the clock source from th e on-chip oscillator clock to the main clock. in low-speed mode, when the main clock is lost while th e cm20 bit is set to 1, an oscillation stop detection interrupt request is generated, and the on-chip oscillator starts oscillating. the sub clock remains as the source for the cpu clock. the on-chip oscillator clock becomes the source for the peripheral function clocks. when the peripheral function clocks ar e stopped, the oscillation stop detect function cannot be used. to enter wait mode while using the oscillation stop detect function, set the cm02 bit in the cm0 register to 0 (peripheral clocks do not stop in wait mode). the oscillation stop detect function is a precaution against th e unintended termination of the main clock by an external factor. set the cm20 bit to 0 (oscillation stop detect function not used) when the main clock is stopped by program, i.e., entering stop mode or setting the cm 05 bit in the cm0 register to 1 (main clock stops). when the main clock frequency is 2 mhz or lower, the os cillation stop detect function is not available. in this case, set the cm20 bit to 0. cm2 register pm2 register applications cm21 pm22 pm27, pm26 1 0 00b clock source for the cpu clock and peripheral function clock 0 1 00b count source for the watchdog timer (the clock keeps running in stop mode.) 0 0 10b clock source for f2n m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 81 of 352 rej09b0385-0100 figure 9.11 procedure to switch from on-chip oscillator clock to main clock 9.1.4 pll clock the pll frequency synthesizer generates the pll clock by multiplying the main clock. the pll clock can be used as the clock source for the cpu clock and peripheral function clocks. the pll frequency synthesizer is stopped after reset. wh en the plc07 bit in the plc0 register is set to 1 (pll runs), the pll frequency synthesizer starts operating. waiting time, tsu(pll) , is required before the pll clock is stabilized. the pll clock is the vco clock divided by either 2 or 3. when the pll clock is used as the clock source for the cpu clock or peripheral function clocks, set each bit as shown in table 9.3. figure 9.12 shows the procedure to use the pll clock as the cpu clock source. set the cm17 bit in the cm1 register to 0 (main clock as cpu clock source) and the plc07 bit to 0 (pll stops) before stopping the cpu clock or the main clock. start end prcr register: prc0 bit = 1 verified several times? 0 (main clock oscillates) mcd register: bits mcd4 to mcd0 = 01000b cm2 register: cm22 bit = 0 cm2 register: cm21 bit = 0 prc0 bit = 0 yes 1 (main clock stops) no divide-by-8 mode loss of the main clock is not detected select the main clock as the cpu clock source disable writing to registers associated with clocks enable writing to registers associated with clocks read the cm23 bit in the cm2 register m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 82 of 352 rej09b0385-0100 table 9.3 bit settings to use pll clock as cpu clock source figure 9.12 procedure to use pll clock as cpu clock source multiplication factor plc0 register plc1 register pll clock plc02 bit plc01 bit plc00 bit plc12 bit 2 011 1 fpll = 2 fxin 3 0 fpll = 3 fxin 8/3 100 1 fpll = 8/3 fxin 4 0 fpll = 4 fxin start end set registers plc0 and plc1 prcr register: prc0 bit = 1 plc0 register: plc07 bit = 1 cm1 register : cm17 bit = 1 prc0 bit = 0 wait for tsu(pll) enable writing to registers associated with clocks cm2 register: cm21 bit = 0 cm0 register: cm07 bit = 0 select the main clock as the cpu clock source (set after a main clock oscillation stabilizes) select the multiplication factor for the pll clock (set registers plc0 and plc1 simultaneously in 16-bit units) plc1 plc0 multiplication factor for pll clock 00000010 01010011b 6/2 = 3 00000010 01010100b 8/2 = 4 00000110 01010011b 6/3 = 2 00000110 01010100b 8/3 = 2.66 pll runs select the pll clock as the cl ock source for the cpu clock and peripheral function clock disable writing to registers associated with clocks wait for pll frequency synthesizer to stabilize m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 83 of 352 rej09b0385-0100 9.2 cpu clock and bclk the cpu clock is used to operate the cpu and also used as the count source for the watchdog timer. after reset, the cpu clock is the main clock divided by eight. the bu s clock (bclk) has the same frequency as the cpu clock and can be output from the bclk pin in microprocessor mode. refer to 9.4 clock output function for details. the main clock, sub clock, on-chip oscillator clock, or pll clock can be selected as the clock source for the cpu clock. when the main clock, on-chip oscillator clock, or pll clock is selected as the clock source for the cpu clock, the selected clock source divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 becomes the cpu clock. bits mcd4 to mcd0 in the mcd register select the clock divisi on. when the mcu enters stop mode or low-power consumption mode, bits mcd4 to mcd0 are set to 01000b (divide-by-8 mode ). therefore, when the cpu clock source is switched to the main clock next time, the cpu clock is the main clock divided by eight. refer to 9.5 power consumption control for details. 9.3 peripheral function clock the peripheral function clocks are used to operate the pe ripheral functions excluding the watchdog timer. the clock selected by the cm17 bit in the cm1 register and the cm21 bit in the cm2 register (any of the main clock, pll clock, or on-chip oscillator clock) becomes the peripheral function clock source (fpfc). 9.3.1 f1, f8, f32, and f2n f1, f8 and f32 are fpfc divided by 1, 8, or 32. bits pm27 and pm 26 in the pm2 register select a f2n clock source from fpfc, xin clock (fxind), and the on- chip oscillator clock (froc). bits cnt3 to cnt0 in the tcspr register select a f2n division. (n = 1 to 15. no division when n = 0.) when wait mode is entered while the cm02 bit in the cm 0 register is set to 1 (peripheral clocks stop in wait mode) or when the cm05 bit is set to 1 using the ma in clock as the peripheral function clock source, fpfc stops. when bits pm27 and pm26 in the pm2 register ar e set to 10b (on-chip oscillator is selected for the f2n clock source), f2n does not stop in wait mode. f1, f8, and f2n are used to operate the serial interface and also is used as the count source for timer a and timer b. the clkout pin outputs f8 and f32. refer to 9.4 clock output function for details. 9.3.2 fad fad is used to operate the a/d converter and has the same frequency as fpfc. when wait mode is entered while the cm02 bit in the cm 0 register is set to 1 (peripheral clocks stop in wait mode) or when the cm05 bit is set to 1 using the main clock as the peripheral function clock source, fad stops. 9.3.3 fc32 fc32 is the sub clock divided by 32. fc32 is used as th e count source for timer a and timer b. fc32 is available if the sub clock is running. m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 84 of 352 rej09b0385-0100 9.4 clock output function the clkout pin outputs fc, f8, or f32. the bclk clock, which has the same frequency as the cpu clock, can be output from the bclk pin in microprocessor mode. table 9.4 lists clkout pin function in microprocessor mode. table 9.4 clkout pin function in microprocessor mode ? : can be set to either 0 or 1 notes: 1. change the cm0 register after setting the prc0 bit in the prcr register to 1 (write enable). 2. change registers pm0 and pm1 after setting the prc1 bit in the prcr register to 1 (write enable). cm0 register (1) pm1 register (2) pm0 register (2) clkout/bclk/al e pin function bits cm01 and cm00 bits pm15 and pm14 pm07 bit 00b 00b 10b 11b 0 outputs bclk 1 outputs ?l? (does not function as p5_3) 01b ? outputs ale 01b ? ? outputs fc 10b ? ? outputs f8 11b ?? outputs f32 m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 85 of 352 rej09b0385-0100 9.5 power consumption control the power consumption control is enabled by controlli ng a cpu clock frequency. the higher the cpu clock frequency is, the more the processing power is available. the lower the cpu clock frequency is, the less power is consumed. when unnecessary oscill ation circuits are stopped, power consumption is further reduced. cpu operating mode, wait mode, and stop mode are provid ed as the power consumption control. cpu operating mode is further separated into the following modes; main clock mode, pll mode, low-speed mode, low-power consumption mode, on-chip oscillator mode, and on-chip oscillator low- power consumption mode. figure 9.13 shows a mode transition diagram. figure 9.13 mode transition 9.5.1 cpu operating mode the cpu clock can be selected from th e main clock, sub clock, on-chip oscillator clock, or pll clock. when switching the cpu clock source, wait until the new cpu clock source stabilizes. to change the cpu clock source from the sub clock, on-chip oscillator clock, or pll clock, set it to the main clock once and then switch it to another clock. to switch the cpu clock source from the on-chip oscillator clock to the main clock, set bits mcd4 to mcd0 in the mcd register to 01000b (divided-by- 8 mode) in on-chip oscillator mode. table 9.5 lists bit setting and operation mode associated with clocks. stop mode reset sub clock on-chip oscillator clock pll clock cm10 = 1 interrupt w a i t i n s t r u c t i o n i n t e r r u p t (note 1) cm10: bit in the cm1 register note: 1. bits mcd4 to mcd0 in the mcd register become 01000b (divide- by-8 mode) after reset. main clock mode wait mode w a i t i n s t r u c t i o n i n t e r r u p t low-power consumption mode low-speed mode on-chip oscillator mode on-chip oscillator low-power consumption mode pll mode wait instruction interrupt m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 86 of 352 rej09b0385-0100 9.5.1.1 main clock mode the main clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the cpu clock. the main clock is also used as the source for fpfc. when the sub clock is running, fc32 can be used as the count source for timer a and timer b. 9.5.1.2 pll mode the pll clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the cpu clock. the pll clock is also used as the source for fpfc. wh en the sub clock is running, fc32 can be used as the count source for timer a and timer b. 9.5.1.3 low-speed mode the sub clock is used as the source for the cpu clock. th e main clock, pll clock, or on-chip oscillator clock is used as the source for fpfc. fc32 can be used as the count source for timer a and timer b. 9.5.1.4 low-power consumption mode the mcu enters low-power consumptio n mode when the main clock stops in low-speed mode. the sub clock is used as the source for the cpu clock, and the on-chip oscillator clock is used as the source for fpfc. fc32 can be used as the count source for timer a and timer b. in low-power consumption mode, bits mcd4 to mcd0 in the mcd register become 01000b (divide-by-8 mode). therefore, next time the cpu clock source is switched to the main clock, the cpu clock is the main clock divided by eight. 9.5.1.5 on-chip oscillator mode the on-chip oscillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the cpu clock. the on-chip os cillator clock is also used as the sour ce for fpfc. when the sub clock is running, fc32 can be used as the coun t source for timer a and timer b. 9.5.1.6 on-chip oscillator low-power consumption mode the mcu enters on-chip oscillator low-power consumpt ion mode when the main clock stops in on-chip oscillator mode. the on-chip os cillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the cpu clock. the on-c hip oscillator clock is also used as the source for fpfc. when the sub clock is running, fc32 can be used as the count source for timer a and timer b. m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 87 of 352 rej09b0385-0100 table 9.5 operation mode setting ? : can be set to either 0 or 1 note: 1. the cm21 bit in the cm2 register has both t he oscillation control and selector functions. 9.5.2 wait mode in wait mode, the cpu and watchdog timer stop operating. if the pm22 bit in the pm2 register is set to 1 (on- chip oscillator clock as watchdog timer count source), the watchdog timer continues operating. since the main clock, sub clock, and on-chip oscillator clock continue running, peripheral functions using these clocks as their clock source also continue to operate. 9.5.2.1 peripheral functi on clock stop function if the cm02 bit in the cm0 register is set to 1 (periphera l clocks stop in wait mode), fad, f1, f8, and f32 stop in wait mode. f2n, which uses the clock selected by the cm 21 bit in the cm2 register as its clock source, also stops in wait mode. power consumption can be reduced by stopping these peripheral clocks. f2n, which uses the xin clock (fxind) or on-ch ip oscillator clock as its clock source, an d fc32 do not stop even in wait mode. 9.5.2.2 entering wait mode to enter wait mode with the cm02 bit in the cm0 regi ster set to 1, set bits mcd4 to mcd0 in the mcd register for the cpu clock frequency to be 10 mhz or less after dividing the main clock. figure 9.14 shows a procedure to enter wait mode. cpu clock source operating mode oscillation control selector cm0 register plc0 register cm2 register cm1 register cm0 register cm05 cm04 plc07 cm21 (1) cm17 cm07 main clock main clock mode 0 ?? 000 pll clock pll mode 0 ? 1010 sub clock low-speed mode 0 1 ??? 1 low power consumption mode 110 ? 01 on-chip oscillator clock on-chip oscillator mode 0 ?? 1 ? 0 on-chip oscillator low- power consumption mode 1 ? 0100 m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 88 of 352 rej09b0385-0100 figure 9.14 procedure to enter wait mode set an interrupt priority level of each interrupt rlvl register: bits rlvl2 to rlvl0 = 7 set the interrupt priority level (ilvl2 to ilvl0) of the interrupt used to exit wait mode i flag = 0 (1) initial setting set the interrupt priority level of the interrupts, which are not used to exit wait mode, to 0 flg register: set ipl bits rlvl2 to rlvl0 = the same level as ipl select the operating mode from the following: -main clock mode -low-speed mode -on-chip oscillator mode -on-chip oscillator low-power consumption mode i flag = 1 execute the wait instruction (2) before entering wait mode wait mode rlvl register: bits rlvl2 to rlvl0 = 7 (3) after exiting wait mode > ipl* = (rlvl2 to rlvl0)* start end initial setting for the wait/stop mode exit interrupt priority level interrupt disabled (ilvl2 to ilvl0) set the processor interrupt priority level (ipl)* set the exit interrupt priority level (rlvl2 to rlvl0)* interrupt enabled set the exit priority level as soon as exiting wait mode (note) insert at least 4 nop' s after wait instruction. when the cm02 bit in the cm0 register is 1, set bits mcd4 to mcd0 in the mcd register for the cpu frequency to be 10 mhz or less. m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 89 of 352 rej09b0385-0100 9.5.2.3 pin states in wait mode table 9.6 lists pin states in wait mode. table 9.6 pin states in wait mode 9.5.2.4 exiting wait mode wait mode is exited by the hardware reset 1, hardware reset 2, nmi interrupt, vdet4 detection interrupt, or peripheral function interrupts. as for a peripheral function interrupt that is not used to exit wait mode, set bits ilvl2 to ilvl0 in the interrupt control register for the peripheral function interrupt to 000b (interrupt disabled) before executing the wait instruction. the cm02 bit setting in the cm0 regist er affects the use of the peripheral function interrupts to exit wait mode. when the cm02 bit is set to 0 (peripheral clocks do no t stop in wait mode), any peripheral function interrupts can be used to exit wait mode. when the cm02 bit is set to 1 (peripheral clocks stop in wait mode), the peripheral functions clocked by the peripheral function clocks stop, and therefore, the peripheral function interrupts cannot be used to exit wait mode. however, the peripheral functions cloc ked by the external clock and fc32 do not stop regardless of the cm02 bit setting. also, f2n, whic h uses the xin clock (fxind) or on- chip oscillator clock as its clock source does not st op. the interrupts generated by the peripheral functions which operate using these clocks can be used to exit wait mode. when the mcu exits wait mode by the peripheral function interrupts or nmi interrupt, the cpu clock does not change before and after the wa it instruction is executed. table 9.7 lists interrupts to be used to exit wait mode and usage conditions. pin states address bus, data bus, cs0 to cs3 , bhe maintain the state immediately before entering wait mode rd , wr , wrl , wrh ?h? hlda , bclk ?h? ale ?l? ports maintain the state immediately before entering wait mode clkout when fc is selected continue to output the clock when f8, f32 are selected ? when the cm02 bit in the cm0 re gister is 0 (peripheral clocks do not stop in wait mode): continue to output the clock ? when the cm02 bit is 1 (peripher al clocks stop in wait mode): the clock is stopped and holds the level immediately before entering wait mode m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 90 of 352 rej09b0385-0100 table 9.7 interrupts to exit wait mode and usage conditions 9.5.3 stop mode in stop mode, all clocks are stopped. since the cpu cl ock and peripheral function clocks are stopped, the cpu and the peripheral functions which are operated by these clocks stop their operation. the least power is required to operate the mcu in stop mode. enter stop mode from main clock mode. 9.5.3.1 entering stop mode stop mode is entered when setting the cm10 bit in the cm1 register to 1 (all clocks stop) while the nmi pin is held ?h?. also, bits mcd4 to mcd0 in the mcd regi ster become 01000b (divide-by-8 mode) by setting the cm10 bit to 1. figure 9.15 shows a procedure to enter stop mode. when entering stop mode, the instructions following cm 10 = 1 instruction are stored into the instruction queue, and the program stops. when stop mode is exited, the instruction lined in the queue is executed before the exit interrupt routine is handled. insert the jmp.b instruction as follows after the instruction to set the cm10 bit to 1. fset i ; i flag is set to 1 bset 0, cm1 ; all clocks stopped (stop mode) jmp.b label_001 ; jmp.b instruction executed (no instruction between jmp.b and label.) label_001: nop ; nop(1) nop ; nop(2) nop ; nop(3) nop ; nop(4) mov.b #0, prcr ; protection set . . . interrupt when cm02 = 0 when cm02 = 1 nmi interrupt available available vdet4 detection interrupt available available serial interface interrupt available when the source clock is the internal clock or clock input to the clki pin. available when the source clock is the clock input to the clki pin or f2n (when fxind or on-chip oscillator clock is selected). key input interrupt available available a/d conversion interrupt available in one-shot mode or single- sweep mode not available timer a interrupt timer b interrupt available in all modes available in event counter mode or when the count source is fc32 or f2n (when fxind or on-chip oscillator clock is selected) int interrupt available available m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 91 of 352 rej09b0385-0100 figure 9.15 procedure to enter stop mode set an interrupt priority level of each interrupt rlvl register: bits rlvl2 to rlvl0 = 7 set the interrupt priority level (ilvl2 to ilvl0) of the interrupt used to exit stop mode i flag = 0 (1) initial setting set the interrupt priority level of the interrupts, which is not used to exit stop mode, to 0 flg register: set ipl bits rlvl2 to rlvl0 = the same level as ipl i flag = 1 cm1 register: cm10 bit = 1 (2) before entering stop mode stop mode rlvl register: bits rlvl2 to rlvl0 = 7 (3) after exiting wait mode prcr register: prc0 bit = 1 prc1 bit = 1 cm2 register: cm20 bit = 0 when the oscillation stop detect function is used cm1 register: cm17 bit = 0 cm2 register: cm21 bit = 0 cm0 register: cm07 bit = 0 select the main clock as the cpu clock source (set after a main clock oscillation stabilizes) start end set the wait/stop mode exit interrupt priority level to 7. interrupt disabled set the exit interrupt priority level (rlvl2 to rlvl0)* enable writing to registers associated with clocks disable oscillation stop detect function interrupt enabled all clocks stop (1) set the exit priority level as soon as exiting wait mode > ipl* = (rlvl2 to rlvl0)* (ilvl2 to ilvl0) set the processor interrupt priority level (ipl)* note: 1. insert the jmp.b instruc tion as follows after the instr uction to set the cm10 bit to 1. bset 0, cm1 ; all clocks stopped (stop mode) jmp.b label_001 ; jmp.b instruction executed (no instruction label_001: ; between jmp.b and label.) nop ; nop(1) nop ; nop(2) nop ; nop(3) nop ; nop(4) mov.b #0, prcr ; protection set . . . m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 92 of 352 rej09b0385-0100 9.5.3.2 pin states in stop mode table 9.8 lists pin states in stop mode. table 9.8 pin states in stop mode 9.5.3.3 exiting stop mode stop mode is exited by the hardware reset 1, nmi interrupt, vdet4 detection interrupt, or peripheral function interrupts. the following are the peripheral function interrupts that can be used to exit stop mode. ? key input interrupt ? int interrupt ? timer a and timer b interrupts (available when the timer counts external pulse having 100-hz frequency or below in event counter mode) when only the hardware reset 1, nmi interrupt, or vdet4 detection interrupt are used to exit stop mode, set bits ilvl2 to ilvl0 in the interrupt control registers fo r all the peripheral function interrupts to 000b (interrupt disabled) before setting the cm10 bit in the cm1 register to 1 (all clocks stop). if the voltage applied to pins vcc1 and vcc2 drops below 3.0 v in stop mode, exit stop mode by the hardware reset 1 after the voltage has satisfied the recommended operating conditions. pin states address bus, data bus, cs0 to cs3 , bhe maintain the state immediately before entering stop mode rd , wr , wrl , wrh ?h? hlda , bclk ?h? ale ?h? ports maintain the state immediately before entering stop mode clkout when fc is selected ?h? when f8, f32 are selected the clock is stopped and holds the level immediately before entering stop mode xin placed in a high-impedance state xout ?h? xcin, xcout placed in a high-impedance state m32c/8a group 9. clock generation circuits rev.1.00 jul 15, 2007 page 93 of 352 rej09b0385-0100 9.6 system clock protect function the system clock protect function prohibits changing the cp u clock source when the main clock is selected as the cpu clock source. with this function, the cpu clock can continue running even if the program runs out of control. when the pm21 bit in the pm2 register is set to 1 (disables a clock change), the following bits cannot be written: ? bits cm02, cm05, and cm07 in the cm0 register ? bits cm10 and cm17 in the cm1 register ? the cm20 bit in the cm2 register ? all bits in registers plc0 and plc1 the cpu clock continues running when the wait instruction is executed. figure 9.16 shows a procedure to use the system clock protect function. follow the procedure while the cm05 bit in the cm0 register is set to 0 (main clock oscillates) and the cm07 bit to 0 (main clock as cpu clock source). figure 9.16 procedure to use system clock protect function start pm2 register: pm21 bit = 1 (1) prcr register: prc1 bit = 0 end prcr register: prc1 bit = 1 enable writing to registers associated with clocks note: 1. execute the wait instruction when the pm21 bit in the pm2 re gister is set to 0. disable a clock change disable writing to registers associated with clocks m32c/8a group 10. protection rev.1.00 jul 15, 2007 page 94 of 352 rej09b0385-0100 10. protection the function protects important registers from being inadvert ently overwritten in case of a program crash. figure 10.1 shows the prcr register. the prc2 bit in the prcr register become s 0 (write disable) by a write to the sfr area after the prc2 bit is set to 1 (write enable). set the pd9 or ps3 regist er immediately after the prc2 bit is set to 1. do not generate an interrupt or a dma or dmacii transfer between these two instruc tions. bits prc0, prc1, and prc3 do not become 0 automatically even after a write to the sfr area. set bits prc0 , prc1, and prc3 to 0 by program. figure 10.1 prcr register b7 b6 b5 b4 b1 b2 b3 protect register symbol prcr address 000ah bit symbol bit name rw after reset xxxx 0000b b0 function prc0 rw prc1 prc2 prc3 rw rw rw writing to registers cm0, cm1, cm2, mcd, plc0, and plc1 is enabled 0: write disable 1: write enable protect bit 0 (1) protect bit 1 (1) writing to registers pm0, pm1, pm2, invc0, and invc1 is enabled 0: write disable 1: write enable protect bit 2 (2) writing to registers pd9 and ps3 is enabled 0: write disable 1: write enable protect bit 3 (1) writing to registers vcr2 and d4int is enabled 0: write disable 1: write enable unimplemented. write 0. read as undefined value. ? (b7-b4) ? notes: 1. bits prc0, prc1 , and prc3 do not bec ome 0 automatically even after a write to the sfr area. set bits prc0, prc1, and prc3 to 0 by program. 2. the prc2 bit becomes 0 by a write to the sfr area after the prc2 bit is set to 1. m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 95 of 352 rej09b0385-0100 11. interrupts 11.1 types of interrupts figure 11.1 shows the types of interrupts. figure 11.1 interrupts ? maskable interrupts the i flag and ipl can enable and disable these interrupts. the interrupt priority order can be ch anged based on interrupt priority level. ? non-maskable interrupt these interrupts cannot be disabled rega rdless of the i flag and ipl settings. interrupts software (non-maskable interrupts) hardware undefined instruction (und instruction) overflow (into instruction) brk instruction brk2 instruction (2) int instruction special (non-maskable interrupts) peripheral function (1) (maskable interrupts) nmi watchdog timer oscillation stop detection vdet4 detection single step (2) address match dmacii transfer complete notes: 1. peripheral function interrupts are generated by the on-chip peripheral functions in the mcu. 2. do not use these interrupts. they are for use with development tool only. m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 96 of 352 rej09b0385-0100 11.2 software interrupts software interrupts occur when part icular instructions are executed. software inte rrupts are non-maskable. 11.2.1 undefined instruction interrupt the undefined instruction interrupt occurs when the und instruction is executed. 11.2.2 overflow interrupt the overflow interrupt occurs when the into inst ruction is executed while the o fl ag in the flg register is 1 (arithmetic operation overflow). instructions that can set the o flag are: abs, adc, adcf, add, addx, cmp, cmpx, div, divu, divx, neg, rmpa, sbb, scmpu, sha, sub, subx 11.2.3 brk interrupt the brk interrupt occurs when the brk instruction is executed. 11.2.4 brk2 interrupt the brk2 interrupt occurs when the brk2 instruction is executed. do not use this interrupt. this is for use with development support tool only. 11.2.5 int instruction interrupt the int instruction interrupt occurs when the int inst ruction is executed. the int instruction can specify software interrupt numbers 0 to 63. so ftware interrupt numbers 8 to 43 are a ssigned to the vector table used for the peripheral function interrupt. this means that the mcu is able to execute the peripheral function interrupt routine by executing the int instruction. when the int in struction is executed, values in the flg register and pc are saved to the stack. the relocat able vector of the specified software interrupt number is stored in pc. the stack, where the data is saved, varies depending on a software interrupt number. isp is selected for software interrupt numbers 0 to 31 . (the u flag in the flg register becomes 0.) for software interrupt numbers 32 to 63, sp which is selected immediately before executing the int instruction is used. (the u flag does not change.) for the peripheral function interrupt, the flg register value is saved and the u flag becomes 0 (isp selected) when an interrupt request is acknowledged. therefore, for software interrupt numbers 32 to 43, sp to be used can differ depending on whether an interrupt is generate d by a peripheral function or by the int instruction. m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 97 of 352 rej09b0385-0100 11.3 hardware interrupts special interrupts and peripheral function interrupts are available as hardware interrupts. 11.3.1 special interrupts special interrupts are non-maskable. 11.3.1.1 nmi interrupt the nmi interrupt occurs when a signal applied to the nmi pin changes from high level (?h?) to low level (?l?). refer to 11.8 nmi interrupt for details. 11.3.1.2 watchdog timer interrupt the watchdog timer interrupt occurs when the watchdog timer counter underflows. refer to 12. watchdog timer for details. 11.3.1.3 oscillation stop detection interrupt the oscillation stop detection interrupt occurs when th e mcu detects a loss of the main clock. refer to 9. clock generation circuits for details. 11.3.1.4 vdet4 detection interrupt the vdet4 detection interrupt occurs when the voltage applied to vcc1 rises above or drops below vdet4. refer to 6.2 vdet4 detection function for details. 11.3.1.5 single-step interrupt do not use the single-step interrupt. this is for use with development support tool only. 11.3.1.6 address match interrupt when the aieri bit in the aier register is set to 1 (address match interrupt enabled), the address match interrupt occurs immediately before executing the inst ruction stored in the address indicated by the rmadi register (i = 0 to 7) . set the starting address of the instruction in the rmadi register. the address match interrupt does not occur if a table data or any address other than the starti ng address of the instruction is set. refer to 11.10 address match interrupt for details. 11.3.2 dmacii transfer complete interrupt the dmacii transfer complete interrupt is generated by the dmacii function. refer to 14. dmacii for details. 11.3.3 peripheral function interrupt the peripheral function interrupt is generated by th e on-chip peripheral functions . the peripheral function interrupts and software interrupt numbers 8 to 43 for the int instruction use the same interrupt vector table. the peripheral function interrupt is maskable. see tables 11.2 and 11.3 for the peripheral function interrupt sources . refer to the descriptions of individual peripheral functions for details. m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 98 of 352 rej09b0385-0100 11.4 high-speed interrupt the high-speed interrupt executes an in terrupt sequence in five cycles and returns from the interrupt routine in three cycles. when the fsit bit in the rlvl register is set to 1 (interrupt priority level 7 is used for the high- speed interrupt), the interrupt that bits ilvl2 to ilvl0 in the interrupt control register are set to 111b (level 7) becomes the high-speed interrupt. only one interrupt can be set as the high-speed interrupt. to use the hi gh-speed interrupt, do not set multiple interrupts to interrupt priority level 7. set the dmaii b it in the rlvl register to 0 (interrupt priority level 7 is used for interrupt) to use the high-speed interrupt. set the starting address of a high-speed interrupt routine in the vct register. when the high-speed interrupt is acknowledged, the flg register value is saved into the svf register and the pc value is saved into the svp register. a program is executed from an address indicated by the vct register. use the freit instruction to return from a high-speed interrupt routine. values saved into registers svf and svp are restored to the flg register and pc by executing the freit instruction. the high-speed interrupt, and dma2 and dma3 share so me of the registers. when using the high-speed interrupt, neither dma2 nor dma3 is available. dma0 and dma1 can still be used. figure 11.2 shows a procedure to use high-speed interrupt. figure 11.2 procedure to use high-speed interrupt i flag = 0 rlvl register: fsit bit = 1 dmaii bit = 0 i flag = 1 operate peripheral functions vct regsiter: set the starting address of the high-speed interrupt routine interrupt control register: bits ilvl2 to ilvl0 = 111b (level 7) interrupt enabled interrupt disabled interrupt priority level 7 is use d for the high-speed interrupt interrupt priority level 7 is used for interrupt set the interrupt priority level in the interrupt control regis ter for the peripheral function used for the high-speed interrupt source. set the peripheral function used for the high-speed interrupt source start end m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 99 of 352 rej09b0385-0100 11.5 interrupts and interrupt vectors there are four bytes in each interrupt ve ctor. set the starting addr ess of an interrupt routin e in each interrupt vector. when an interrupt request is acknowledged, an interrupt routine is executed from the address set in its interrupt vector. figure 11.3 shows an interrupt vector. figure 11.3 interrupt vector 11.5.1 fixed vector table the fixed vector table is allocated addresses ffffdch to ffffffh. table 11.1 lists the fixed vector table. table 11.1 fixed vector table 11.5.2 relocatable vector table the relocatable vector table occupies 256 bytes beginning from the address set in the intb register. tables 11.2 and 11.3 list the relocatable vector table. set an even address to the starting address of the vector set in the intb register to increase the interrupt sequence execution rate. interrupt source vector addresses address (l) to address (h) remarks reference undefined instruction ffffdch to ffffdfh m32c/80 series software manual overflow ffffe0h to ffffe3h brk instruction ffffe4h to ffffe7h if the content of the address ffffe7h is ffh, the cpu executes from the address stored into software interrupt number 0 in the relocatable vector table. address match ffffe8h to ffffebh ? ffffech to ffffefh reserved space watchdog timer fffff0h to fffff3h these addresses are used for the watchdog timer interrupt, oscillation stop detection interrupt, and vdet4 detection interrupt. reset, clock generation circuit, watchdog timer ? fffff4h to fffff7h reserved space nmi fffff8h to fffffbh reset fffffch to ffffffh reset 8 middle-order bits of address 8 low-order bits of address 00h vector address+0 lsb msb vector address+1 vector address+2 vector address+3 8 high-order bits of address m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 100 of 352 rej09b0385-0100 table 11.2 relocatable vector tables (1) notes: 1. these are the address offset from the base address set in the intb register. 2. the i flag does not disable this interrupt. 3. in i 2 c mode, nack, ack, or start/stop condition detection can be the interrupt sources. interrupt source vector table address address (l) to address (h) (1) software interrupt number reference brk instruction (2) +0 to +3 (0000h to 0003h) 0 m32c/80 series software manual reserved space +4 to +31 (0004h to 001fh) 1 to 7 dma0 +32 to +35 (0020h to 0023h) 8 dmac dma1 +36 to +39 (0024h to 0027h) 9 dma2 +40 to +43 (0028h to 002bh) 10 dma3 +44 to +47 (002ch to 002fh) 11 timer a0 +48 to +51 (0030h to 0033h) 12 timer a timer a1 +52 to +55 (0034h to 0037h) 13 timer a2 +56 to +59 (0038h to 003bh) 14 timer a3 +60 to +63 (003ch to 003fh) 15 timer a4 +64 to +67 (0040h to 0043h) 16 uart0 transmission, nack (3) +68 to +71 (0044h to 0047h) 17 serial interfaces uart0 reception, ack (3) +72 to +75 (0048h to 004bh) 18 uart1 transmission, nack (3) +76 to +79 (004ch to 004fh) 19 uart1 reception, ack (3) +80 to +83 (0050h to 0053h) 20 timer b0 +84 to +87 (0054h to 0057h) 21 timer b timer b1 +88 to +91 (0058h to 005bh) 22 timer b2 +92 to +95 (005ch to 005fh) 23 timer b3 +96 to +99 (0060h to 0063h) 24 timer b4 +100 to +103 (0064h to 0067h) 25 int5 +104 to +107 (0068h to 006bh) 26 interrupts int4 +108 to +111 (006ch to 006fh) 27 int3 +112 to +115 (0070h to 0073h) 28 int2 +116 to +119 (0074h to 0077h) 29 int1 +120 to +123 (0078h to 007bh) 30 int0 +124 to +127 (007ch to 007fh) 31 timer b5 +128 to +131 (0080h to 0083h) 32 timer b uart2 transmission, nack (3) +132 to +135 (0084h to 0087h) 33 serial interfaces uart2 reception, ack (3) +136 to +139 (0088h to 008bh) 34 uart3 transmission, nack (3) +140 to +143 (008ch to 008fh) 35 uart3 reception, ack (3) +144 to +147 (0090h to 0093h) 36 uart4 transmission, nack (3) +148 to +151 (0094h to 0097h) 37 uart4 reception, ack (3) +152 to +155 (0098h to 009bh) 38 m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 101 of 352 rej09b0385-0100 table 11.3 relocatable vector tables (2) notes: 1. these are the address offset from the base address set in the intb register. 2. the i flag does not disable this interrupt. 3. in i 2 c mode, nack, ack, or start/stop condition detection can be the interrupt sources. 4. the ifsr6 bit in the ifsr register selects either ua rt0 or uart3. the ifsr7 bit selects either uart1 or uart4. interrupt source vector table address address (l) to address (h) (1) software interrupt number reference bus conflict detection, start condition detection/ stop condition detection (uart2) (3) +156 to +159 (009ch to 009fh) 39 serial interfaces bus conflict detection, start condition detection/ stop condition detection (uart3 or uart0) (4) +160 to +163 (00a0h to 00a3h) 40 bus conflict detection, start condition detection/ stop condition detection (uart4 or uart1) (4) +164 to +167 (00a4h to 00a7h) 41 a/d0 +168 to +171 (00a8h to 00abh) 42 a/d converter key input +172 to +175 (00ach to 00afh) 43 interrupts reserved space +176 to +255 (00b0h to 00ffh) 44 to 63 - int instruction (2) +0 to +3 (0000h to 0003h) to +252 to +255 (00fch to 00ffh) 0 to 63 interrupts m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 102 of 352 rej09b0385-0100 11.6 interrupt request acknowledgement software interrupts occur when their corresponding instru ctions are executed. the into instruction, however, requires the o flag in the flg register to be 1. special interrupts occur when their corresponding interrupt requests are generated. for the peripheral function interrupts to be acknowledged, the following conditions must be met: ? i flag = 1 ? ir bit = 1 ? bits ilvl2 to ilvl > ipl the i flag, ipl, ir bit, and bits ilvl 2 to ilvl0 are independent of each other. the i flag and ipl are in the flg register. the ir bit and bits ilvl2 to ilvl0 are in the interrupt control register. 11.6.1 i flag and ipl the i flag enables and disables maskable interrupts. when the i flag is set to 1 (ena ble), all maskable interrupts are enabled; when the i flag is set to 0 (disable), they are disabled. the i flag is automatically set to 0 after reset. ipl is 3 bits wide and indicates the interrupt priority leve l (ipl) from level 0 to level 7. if a requested interrupt has higher priority level than ipl, the interrupt is acknowledged. table 11.4 lists interrupt priority levels associated with ipl. table 11.4 interrupt priority levels 11.6.2 interrupt control re gisters and rlvl register the interrupt control registers are used to control the peripheral function interrupts. figures 11.4 and 11.5 show the interrupt control registers. figure 11.6 shows the rlvl register. ipl2 to ipl0 required interrupt priority levels to be acknowledged for maskable interrupts 0 level 1 and above 1 level 2 and above 2 level 3 and above 3 level 4 and above 4 level 5 and above 5 level 6 and above 6 level 7 and above 7 all maskable interrupts are disabled m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 103 of 352 rej09b0385-0100 figure 11.4 interrupt control register (1) b7 b6 b5 b4 b1 b2 b3 interrupt control register symbol ta0ic to ta4ic tb0ic to tb5ic s0tic to s4tic s0ric to s4ric bcn0ic to bcn4ic dm0ic to dm3ic ad0ic kupic address 006ch, 008ch, 006eh, 008eh, 0070h 0094h, 0076h, 0096h, 0078h, 0098h, 0069h 0090h, 0092h, 0089h, 008bh, 008dh 0072h, 0074h, 006bh, 006dh, 006fh 0071h, 0091h, 008fh, 0071h (1) , 0091h (2) 0068h, 0088h, 006ah, 008ah 0073h 0093h bit symbol bit name rw ilvl0 after reset xxxx x000b xxxx x000b xxxx x000b xxxx x000b xxxx x000b xxxx x000b xxxx x000b xxxx x000b notes: 1. the bcn0ic register shares the address with the bcn3ic register. 2. the bcn1ic register shares the address with the bcn4ic register. 3. the ir bit can be set to 0 only. (do not set to 1.) b0 function interrupt priority level select bits ilvl1 ilvl2 b2 b1 b0 0 0 0: level 0 (interrupt disabled) 0 0 1: level 1 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 ir rw rw rw rw ? (b7-b4) ? interrupt request bit (3) 0: interrupt not requested 1: interrupt requested unimplemented. write 0. read as undefined value. m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 104 of 352 rej09b0385-0100 figure 11.5 interrupt control register (2) 11.6.2.1 bits ilvl2 to ilvl0 bits ilvl2 to ilvl0 determine an interrupt priority level. the higher the interrupt priority level is, the higher priority the interrupt has. when an interrupt request is generated, its interrupt prior ity level is compared to ipl. this interrupt is enabled only when its interrupt priority level is higher than ip l. when bits ilvl2 to ilvl0 are set to 000b (level 0), the interrupt is disabled. 11.6.2.2 ir bit the ir bit is automatically set to 1 (interrupt requeste d) by hardware when an interrupt request is generated. after an interrupt request is acknowle dged and an interrupt sequence in th e corresponding interrupt vector is executed, the ir bit is automatically set to 0 (interrupt not requested) by hardware. the ir bit can be set to 0 by program. do not set it to 1. b7 b6 b5 b4 b1 b2 b3 symbol int0ic to int2ic int3ic to int5ic (1) address 009eh, 007eh, 009ch 007ch, 009ah, 007ah after reset xx00 x000b xx00 x000b b0 function bit symbol bit name rw rw interrupt control register rw rw rw rw rw ilvl0 interrupt priority level select bits ilvl1 ilvl2 b2 b1 b0 0 0 0: level 0 (interrupt disabled) 0 0 1: level 1 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 ir pol lvs interrupt request bit (2) polarity switch bit (3) level sensitive/ edge sensitive switch bit (4) 0 : edge sensitive 1 : level sensitive 0: interrupt not requested 1: interrupt requested 0: falling edge / "l" level selected 1: rising edge / "h" level selected ? (b7-b6) ? unimplemented. write 0. read as undefined value. notes: 1. when a 16-bit data bus is used in microprocessor mode, pi ns int3 to int5 are used as data bus. in this case, set bits ilvl2 to ilvl0 in registers int3ic to int5ic to 000b. 2. the ir bit can be set to 0 only. (do not set to 1.) 3. set the pol bit to 0 when its corresponding bit in the ifsr register is set to 1 (both edges). 4. when the lvs bit is set to 1, set its corresponding bit in the ifsr register to 0 (one edge). m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 105 of 352 rej09b0385-0100 figure 11.6 rlvl register 11.6.2.3 bits rlvl2 to rlvl0 when using an interrupt to exit wait mode or stop mode, refer to 9.5.2 wait mode and 9.5.3 stop mode for details. b7 b6 b5 b4 b1 b2 b3 symbol rlvl address 009f after reset xxxx 0000b b0 function bit symbol bit name rw rw exit priority register rw rw rw rw ? rlvl0 exit wait mode/stop mode interrupt priority level control bits (1) rlvl1 rlvl2 b2 b1 b0 0 0 0: level 0 0 0 1: level 1 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 fsit dmaii high-speed interrupt select bit dmacii select bit (4) 0: interrupt priority level 7 is used for interrupt 1: interrupt priority level 7 is used for dmacii transfer (2) 0: interrupt priority level 7 is used for normal interrupt 1: interrupt priority level 7 is used for high-speed interrupt (2)(3) ? (b7-b6) ? unimplemented. write 0. read as undefined value. notes: 1. the mcu exits stop or wait mode when an interrupt priority level of a requested interrupt is higher than a level set us ing bits rlvl2 to rlvl0. set bits rlvl2 to rlvl0 to the same value as ipl in the flg register. 2. do not set both the fsit and dmaii bits to 1. set either the fsit bit or the dmaii bit to 1 before setting bits ilvl2 to ilvl0 in the interrupt control register to 111b. 3. only one interrupt can have the interrupt priority level 7 when selecting the high-speed interrupt. 4. the dmaii bit is undefined after reset. to use interrupt priority level 7 for an interrupt, set it to 0 before setting the interrupt control register. ? (b4) unimplemented. write 0. read as undefined value. m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 106 of 352 rej09b0385-0100 11.6.3 interrupt sequence the interrupt sequence is performed between an in terrupt request acknowledgment and interrupt routine execution. when an interrupt request is generated while an instruct ion is being executed, the cpu determines its interrupt priority after the instruction in progress is completed. then, the cpu starts the interrupt sequence from the following cycle. however, for the scmpu, si n, smovb, smovf, smo vu, sstr, sout, and rmpa instructions, if an interrupt request is generated whil e one of these instructions is being executed, the mcu suspends the instruction execution to start the interrupt sequence. the interrupt sequence is pe rformed as indicated below: (1) the cpu obtains the interrupt number by reading the address 000000h (address 000002h for the high- speed interrupt). then, the corresponding ir bit to the interrupt becomes 0 (interrupt not requested). (2) the flg register value, immediately before the interrupt sequence, is saved to a temporary register (1) in the cpu. (3) each bit in the flg regi ster becomes as follows: the i flag becomes 0 (interrupt disabled) the d flag becomes 0 (single-step interrupt disabled) the u flag becomes 0 (isp selected) (4) the internal register value (the flg register value saved in (2)) in the cpu is saved to the stack; or to the svf register for the high-speed interrupt. (5) the pc value is saved to the stack; or to the svp register for th e high-speed interrupt. (6) the interrupt priority level of the acknowledged interrupt becomes the ipl level. (7) an interrupt vector corresponding to the acknowledged interrupt is stored into pc. after the interrupt sequence is completed, the cpu executes the instruction from the starting address of the interrupt routine. note: 1. temporary register ca nnot be accessed by users. m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 107 of 352 rej09b0385-0100 11.6.4 interrupt response time figure 11.7 shows the interrupt response time. interru pt response time is the period between an interrupt request generation and the end of an interrupt sequence. interrupt response time is divided into two phases: the period between an interrupt request generation and the end of the ongoing instruction execution ((a) in figure 11.7), and the period required to perform the interrupt sequence ((b) in figure 11.7). figure 11.7 interrupt response time time (a) varies depending on an instruction being exec uted. the div, divx, and divu instructions require the longest time (a), which is at the maximum of 42 cycles. table 11.5 lists time (b). table 11.5 interrupt sequence execution time (1) note: 1. the values when interrupt vectors are allocated in even addresses in the external rom, and when the external bus cycle is two cpu clock cycles. this does not apply to the high-speed interrupt. interrupts execution time (in terms of cpu clock) peripheral function 16 cycles int instruction 14 cycles nmi watchdog timer undefined instruction address match 15 cycles overflow 16 cycles brk instruction (relocatab le vector table) 19 cycles brk instruction (fixed vector table) 21 cycles high-speed interrupt 5 cycles instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request is acknowledged interrupt request is generated (a) period between an interrupt request generation and the end of instruction execution. (b) period required to perform an interrupt sequence. m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 108 of 352 rej09b0385-0100 11.6.5 ipl change when interrupt request is acknowledged when a peripheral function interrupt request is acknowl edged, the priority level for the acknowledged interrupt becomes the ipl level. software interrupts and special interrupt s have no interrupt priority level. if an interrupt that has no interrupt priority level occurs, the value shown in table 11.6 becomes the ipl level. table 11.6 interrupts without inte rrupt priority levels and ipl 11.6.6 saving a register in the interrupt sequence, values of the fl g register and pc are saved to the stack. figure 11.8 shows the stack states before an d after an interrupt request is acknowledged. the other necessary registers are saved by program at the beginning of the inte rrupt routine. the pushm instruction can save multiple registers (1) in the register bank currently used. refer to 11.4 high-speed interrupt for the high-speed interrupt. note: 1. selectable from register s r0, r1, r2, r3, a0, a1, sb, and fb. figure 11.8 stack states before and after acknowledgement of interrupt request interrupt source ipl level watchdog timer, nmi , oscillation stop detection, vdet4 detection 7 software, address match not changed [sp] sp value before an interrupt is generated stack state before an interrupt request is acknowledged stack state before an interrupt request is acknowledged pcl: 8 low-order bits of pc pcm: 8 middle-order bits of pc pch: 8 high-order bits of pc flgl: 8 low-order bits of flg flgh: 8 high-order bits of flg address m m - 1 m - 2 m - 3 m - 4 m + 1 m - 5 m - 6 previous stack contents previous stack contents stack msb lsb 00h flgl previous stack contents pch previous stack contents [sp] new sp value m + 1 address stack pcm pcl msb lsb m - 5 m - 6 m m - 1 m - 2 m - 3 m - 4 flgh m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 109 of 352 rej09b0385-0100 11.6.7 returning from interrupt routine when the reit instruction is executed at the end of an in terrupt routine, the values of the flg register and pc, which have been saved to the stack before the interrupt sequence is performed, are au tomatically restored. and then, the program that was running before an interrupt request was acknowledged, resumes its process. the high-speed interrupt uses the frei t instruction instead. refer to 11.4 high-speed interrupt for details. before executing the reit or freit inst ruction, use the popm instruction or the like to restore registers saved by program in the interrupt routine. by executing the reit or freit instruction, register bank is switched back to the bank used immediat ely before the interrupt sequence. 11.6.8 interrupt priority if two or more interrupt requests ar e detected at the same sampling poin ts (a timing to detect whether any interrupt request is generated or not), the inte rrupt with the highest priority is acknowledged. set bits ilvl2 to ilvl0 in the interrupt control regi ster to select the given priority level for maskable interrupts (peripheral function interrupts). priority levels of special interrupts, such as nmi and watchdog timer interrupt are fixed by hardware. figure 11.9 shows the priority of hardware interrupts. the interrupt priority does not affect software interr upts. executing an instruction for a software interrupt causes the mcu to execute an interrupt routine. figure 11.9 interrupt priority of hardware interrupts 11.6.9 interrupt priority level select circuit the interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt requests are generated at the same sampling point. figure 11.10 shows the interrupt priority level select circuit. h l reset nmi watchdog timer oscillation stop detection vdet4 detection peripheral function address match m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 110 of 352 rej09b0385-0100 figure 11.10 interrupt priority level select circuit dma1 dma2 dma3 timer a0 uart0 transmission/nack uart0 reception/ack uart1 transmission/nack timer b1 timer b2 timer b3 timer b4 int5 int4 int2 int1 int0 timer b5 uart2 transmission/nack uart2 reception/ack ipl i flag dma0 timer a3 timer a4 watchdog timer, oscillation stop detection, vdet4 detection nmi dmacii interrupt request acknowledged (to cpu) level 0 (initial value) interrupt priority level high low peripheral function interrupt priority (if priority levels are the same) timer a1 timer a2 uart1 reception/ack timer b0 int3 uart3 transmission/nack address match interrupt request priority level detection result outputs (to the clock generation circuit) uart3 reception/ack uart4 transmission/nack uart4 reception/ack bus conflict/ start or stop condition detection (uart2) bits rlvl2 to rlvl0 bus conflict/ start or stop condition detection (uart0, uart3) key input interrupt a/d0 bus conflict/ start or stop condition detection (uart1, uart4) interrupt priority level m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 111 of 352 rej09b0385-0100 11.7 int interrupt external input to pins int0 to int 5 generate the int0 to int 5 interrupts. int interrupts can select either edge sensitive, which the rising/falling edge triggers an interrupt request, or level sensitive, which an input signal level to the inti pin (i = 0 to 5) triggers an interrupt request. to use int interrupts with edge sensitive, set the lvs bit in the intiic register to 0 (edge sensitive), and select a rising edge, falling edge, or both edges using the pol bit in the intiic register and the ifsri bit in the ifsr register. when the ifsri bit is set to 1 (both edges), se t the corresponding pol bit to 0 (falling edge). when the selected edge is detected at the inti pin, the corresponding ir bit becomes 1. to use int interrupts with level sensitive, set the lvs bit to 1 (l evel sensitive) and select either ?l? level or ?h? level using the pol bit. also, set the ifsri bit to 0 (one edge). while the selected le vel is detected at the inti pin, the ir bit becomes 1 and remains 1. therefore, the inte rrupt requests are generated repeatedly as long as the selected level is detected to the inti pin. when the input signal is changed to the inactive level, the ir bit becomes 0 by the interrupt request acknowledgement or writing a 0 by program. interrupts can be enabled or disabled using bits ilvl2 toilvl0 in the intiic register. figure 11.11 shows inti interrupt setting procedures (i = 0 to 5). figure 11.12 shows the ifsr register. m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 112 of 352 rej09b0385-0100 figure 11.11 inti interrupt setting procedures (i = 0 to 5) start intiic register: pol bit lvs bit = 0 ifsr register: ifsri bit intiic register: bits ilvl2 to ilvl0 = 000b interrupt disabled select polarity (set to 0 when both edges are selected) select edge sensitive select either one edge or both edge intiic register: ir bit = 0 clear the interrupt request bit end < procedure for edge sensitive > < procedure for level sensitive > i = 0 to 5 start intiic register: pol bit lvs bit = 1 ifsr register: ifsri bit = 0 intiic register: bits ilvl2 to ilvl0 = 000b interrupt disabled select polarity select level sensitive select one edge end intiic register: bits ilvl2 to ilvl0 interrupt enabled intiic register: ir bit = 0 clear the interrupt request bit intiic register: bits ilvl2 to ilvl0 interrupt enabled m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 113 of 352 rej09b0385-0100 figure 11.12 ifsr register b7 b6 b5 b4 b1 b2 b3 external interrupt source select register symbol ifsr address 031fh bit symbol bit name rw after reset 00h b0 function ifsr0 rw 0: one edge 1: both edges int0 interrupt polarity select bit (1) ifsr1 int1 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr2 int2 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr3 int3 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr4 int4 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr5 int5 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr6 uart0, uart3 interrupt source select bit 0: uart3 bus conflict, start condition detection, stop condition detection 1: uart0 bus conflict, start condition detection, stop condition detection rw rw rw rw rw rw ifsr7 uart1, uart4 interrupt source select bit 0: uart4 bus conflict, start condition detection, stop condition detection 1: uart1 bus conflict, start condition detection, stop condition detection rw note: 1. set the ifsri bit (i = 0 to 5) to 0 to select a level-sensitive triggering. when selecting both edges, set the pol bit in the corresponding intilc register to 0 (falling edge). m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 114 of 352 rej09b0385-0100 11.8 nmi interrupt the nmi interrupt is non-maskable. the nmi interrupt occurs when a si gnal applied to the p8_5/nmi pin changes from ?h? level to ?l? level. a read from the p8_5 bit in the p8 register returns the input level of the nmi pin. when the nmi interrupt is not used, connect the nmi pin to vcc1 via a resistor (pull-up). ?h? level or ?l? level width of the signal applied to the nmi pin must be 2 cpu clock cycles + 300 ns or more. 11.9 key input interrupt the ir bit in the kupic register become s 1 when an falling edge is detected at any of the pins p10_4 to p10_7 set to input mode. the key input interrupt can also be used as key-on wake-up function to exit wait mode or stop mode. to use the key input interrupt, do not use pins p10_4 to p10_7 as a/d input. figure 11.13 shows a block diagram of the key input interrupt. when an ?l? signal is applied to one of the pins p10_4 to p10_7 in input mode, an falling edge detected at the other pins is not recognized as an in terrupt request signal. when the psc_7 bit in the psc register is set to 1 (an_4 to an_7), the input buffer for ports or the key input interrupt is disconnected. therefore, the pin level cannot be obtained by r eading the port p10 register in input mode. also, the ir bit in the kupic register does not b ecome 1 even if a falling edge is detected at pins ki0 to ki3 . figure 11.13 key input interrupt key input interrupt request p10_7/ki3 pu31 bit pd10_7 bit pull-up transistor pull-up transistor pull-up transistor pull-up transistor pd10_7 bit pd10_6 bit pd10_5 bit pd10_4 bit p10_6/ki2 p10_5/ki1 p10_4/ki0 psc_7 bit pd10_4 to pd10_7: bits in the pd10 register psc_7: bit in the psc register pu31: bit in the pur3 register m32c/8a group 11. interrupts rev.1.00 jul 15, 2007 page 115 of 352 rej09b0385-0100 11.10 address match interrupt the address match interrupt is non-maskable. this interru pt occurs immediately before executing the instruction stored in the address specifie d by the rmadi register (i=0 to 7). eight addresses can be set for the address match interrupt. the aieri bit in the aier register determ ines whether the interrupt is enabled or disabled. figure 11.14 shows registers associated with the address match interrupt. set the starting address of the instruction in the rmadi re gister. the address match in terrupt does not occur if a table data or any address other than the starting address of the instruction is set. figure 11.14 rmad0 to rmad7 registers, aier register b7 b6 b5 b4 b1 b2 b3 symbol aier address 0009h after reset 00h b0 function bit symbol bit name rw aier5 aier7 address match interrupt 3 enable bit address match interrupt 7 enable bit rw rw rw rw aier4 rw aier3 address match interrupt 5 enable bit address match interrupt 6 enable bit aier6 address match interrupt enable register address match interrupt 4 enable bit address match interrupt 1 enable bit aier1 rw address match interrupt 2 enable bit rw aier2 0: interrupt disabled 1: interrupt enabled address match interrupt 0 enable bit aier0 rw 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled b23 b16 b15 b7 b8 after reset b0 address match interrupt r egister i (i = 0 to 7) symbol rmad0 rmad1 rmad2 rmad3 rmad4 rmad5 rmad6 rmad7 address 0012h to 0010h 0016h to 0014h 001ah to 0018h 001eh to 001ch 002ah to 0028h 002eh to 002ch 003ah to 0038h 003eh to 003ch 000000h 000000h 000000h 000000h 000000h 000000h 000000h 000000h setting range function rw addressing register for the address match interrupt rw 000000h to ffffffh m32c/8a group 12. watchdog timer rev.1.00 jul 15, 2007 page 116 of 352 rej09b0385-0100 12. watchdog timer the watchdog timer is used to detect the program runn ing improperly. the watchdog timer contains a 15-bit free- running counter. if a write to the wdts register is not performed due to a program running out of control, the free- running counter underflows, which results in the watc hdog timer interrupt generation or the mcu reset. when operating the watchdog timer, write to th e wdts register in a shorter cycle than the watchdog timer cycle in such as the main routine. tables 12.1 and 12.2 list specifications of the watchdog timer. figure 12.1 shows a block diagram of the watchdog timer. figures 12.2 and 12.3 show regi sters associated with the watchdog timer. table 12.1 watchdog timer specifications (1) note: 1. the watchdog timer shares the same vector with the o scillation stop detection in terrupt and vdet4 detection interrupt. when using the watchdog timer interrupt simultaneously with these interrupts, determine whether the watchdog timer interrupt is generated by reading the d43 bit in the d4int register in the interrupt rouine. table 12.2 watchdog timer specifications (2) ? : either 0 or 1 fcpu: cpu clock frequency froc: on-chip oscillator clock frequency notes: 1. once the pm22 bit is set to 1, it cannot be set to 0 by program. 2. difference between the calculation result and actual period can be one count source cycle of the counter. 3. a write to the cm10 bit in the cm1 register is disabled . writing a 1 has no effect and the mcu does not enter stop mode. the watchdog timer interrupt cannot be used to exit wait mode. items specifications count operation the free-running counter decrements count start condition writing to the wdts register: a write to the wdts register initializ es a free-running counter and the counter decrements from 7fffh when underflows one of the following occurs (selectable using the cm06 bit in the cm0 register): ? watchdog timer interrupt generation (1) ? mcu reset after underflows the counter continues decrementing (when the watchdog timer interrupt is selected) read from watchdog timer a read from bit 4 to bit 0 in the wdc register returns bit 14 to bit 10 of the free-running counter item bit setting and specifications pm22 bit in pm2 register (1) 0001 cm07 bit in cm0 register 0 0 1 ? wdc7 bit in wdc register 1 0 ?? clock source cpu clock on-chip oscillator clock divided by mcd register sub clock prescaler divide-by-16 divide-by-128 divide-by-2 not available count source for counter 16 128 2 time-out period (formula) (2) 524288 4194304 65536 32768 time-out period (reference) approx. 16.4 ms fcpu = 32 mhz approx. 131.1 ms fcpu = 32 mhz approx. 2 s fcpu = 32 khz approx. 32.8 ms froc = 1 mhz operation in wait mode, stop mode, and hold state stops operates (3) 1 fcpu 1 fcpu 1 fcpu 1 froc 1 fcpu 1 fcpu 1 fcpu 1 froc m32c/8a group 12. watchdog timer rev.1.00 jul 15, 2007 page 117 of 352 rej09b0385-0100 figure 12.1 watchdog timer block diagram 1/16 prescaler cm07=0 wdc7=0 cm06, cm07: bits in the cm0 register wdc7: bit in the wdc register pm22: bit in the pm2 register d43: bit in the d4int register watchdog timer interrupt signal 0 cm07=0 wdc7=1 cm07=1 set to 7fffh watchdog timer on-chip oscillator clock write signal to the wdts register internal reset signal 1/128 1/2 reset cpu clock hold pm22 1 cm06 0 1 vdet4 detection interrupt signal oscillation stop detection interrupt signal d43 watchdog timer interrupt request (non-maskable) wait mode signal m32c/8a group 12. watchdog timer rev.1.00 jul 15, 2007 page 118 of 352 rej09b0385-0100 figure 12.2 cm0 register b7 b6 b5 b4 b1 b2 b3 system clock control register 0 (1) symbol cm0 address 0006h bit symbol bit name rw cm00 after reset 0000 1000b rw notes: 1. set the cm0 register after the prc0 bi t in the prcr register is set to 1 (write enable). 2. the bclk, ale, or "l" signal is output from the p 5_3 pin in microprocessor mode. the p5_3 does not function as an i/o p ort. 3. fc32 does not stop running. 4. to set the cm04 bit to 1, set bits pd8_7 and pd8_6 in the pd8 register to 00b (ports p8_6 and p8_7 in input mode) and t he pu25 bit in the pur2 register to 0 (no pull-up). 5. the cm05 bit stops the main clock oscillation when ent ering low-power consumption mode or on-chip oscillator low-power consumption mode. the cm05 bit cannot be us ed to determine whether the main clock stops or not. to stop the main clock oscillation, set the plc07 bit in the plc0 register to 0 and t he cm05 bit to 1 after setting the cm07 bit to 1 or setting the c m21 bit in the cm2 register to 1 (on-chip oscillator clock). when the cm05 bit is set to 1, the xout pin outputs "h". since an on-chip feedback resistor remains on, the xin pin i s pulled up to the xout pin via the feedback resistor. 6. when the cm05 bit is set to 1, bits mcd4 to mcd0 in the mcd register become 01000b (divide-by-8 mode). in on-chip oscillator mode, bits mcd4 to mcd0 do not become 01000b even if the cm05 bit is set to 1. 7. once the cm06 bit is set to 1, it cannot be set to 0 by program. 8. change the cm07 bit setting from 0 to 1, after t he cm04 bit is set to 1 and the sub clock oscillation stabilizes. change the cm07 bit setting from 1 to 0, after the cm05 bit is set to 0 and the main clock osc illation stabilizes. do not change the cm07 bit simultaneously with the cm04 or cm05 bit. 9. if the pm21 bit in the pm2 register is set to 1 (d isables a clock change), a write to bits cm02, cm05, and cm07 has no effect. 10. when stop mode is entered, the cm03 bit becomes 1. b0 function b1 b0 0 0: i/o port p5_3 (2) 0 1: outputs fc 1 0: outputs f8 1 1: outputs f32 clock output function select bits (2) cm01 cm02 peripheral function clock stop in wait mode bit (9) 0: peripheral clocks do not stop in wait mode 1: peripheral clocks stop in wait mode (3) cm03 xcin-xcout drive capability select bit (10) 0: low 1: high cm04 port xc switch bit 0: i/o port function 1: xcin-xcout oscillation function (4) cm05 main clock (xin-xout) stop bit (5, 9) 0: main clock oscillates 1: main clock stops (6) cm06 watchdog timer function select bit cpu clock select bit 0 (8, 9) 0: watchdog timer interrupt 1: reset (7) cm07 0: clock selected by the cm21 bit divided by the mcd register 1: sub clock rw rw rw rw rw rw rw m32c/8a group 12. watchdog timer rev.1.00 jul 15, 2007 page 119 of 352 rej09b0385-0100 figure 12.3 wdc register, wdts register b7 0 b6 b5 b4 b1 b2 b3 watchdog timer control register symbol wdc address 000fh bit symbol bit name rw ? (b4-b0) after reset 00xx xxxxb b0 function wdc5 ? (b6) cold start/warm start determine flag (1) high-order bits of watchdog timer wdc7 rw reserved bit prescaler select bit rw rw ro 0: cold start 1: warm start set to 0 0: divide-by-16 1: divide-by-128 notes: 1. the wdc5 bit is 0 after power-on. it can be set to 1 only by program. the bit becomes 1 by writing either a 0 or 1. the bit maintains a value set before reset, even after reset has been performed. b7 watchdog timer start register symbol wdts address 000eh rw address undefined b0 function the counter is initialized and starts decrementing by a write instruction to the wdts register. 7fffh is the default value after initializ ation no matter what value is written. wo m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 120 of 352 rej09b0385-0100 13. dmac dmac allows data to be sent to and from memory with out involving the cpu. the m32c/8a group has four dmac channels. dmac transfers a 8- or 16-b it data from a source address to a destin ation address for each transfer request. dma0 and dma1 must be prioritized when using dmac. dma2 and dma3 share the registers with the high-speed interrupts. the high-speed interrupts cannot be us ed when three or more dmac channels are used. the cpu and dmac use the same data bus, but dmac ha s a higher bus access privilege than the cpu. dmac employing the cycle-steal meth od enables a high-speed operation from a tran sfer request to a completion of 16-bit (word) or 8-bit (byte) data transfer. figure 13.1 shows a mapping of dmac-associated registers. table 13.1 lists specifications of dmac. figures 13.2 to 13.6 show dmac-associated registers. figures 13.7 and 13.8 show register settings. because the registers shown in figure 13.1 are allocated in the cpu, use the ldc instruc tion to set the registers. to set registers dct2, dct3, drc2, drc3, dma2, and dma3 , set the b flag to 1 (register bank 1) and write to registers r0 to r3, a0, and a1 with the mov instruction. to set registers dsa2 and dsa3, set the b flag to 1 and write to registers sb and fb with the ldc instruction. to set registers dra2 and dra3, write to re gisters svp and vct with the ldc instruction. figure 13.1 register mapping for dmac dma mode register 0 dma mode register 1 dma0 transfer count register dma1 transfer count register dma0 transfer count reload register (1) dma1 transfer count reload register (1) dma0 memory address register dma1 memory address register dma0 sfr address register dma1 sfr address register dma0 memory address reload register (1) dma1 memory address reload register (1) dmac-associated registers when three or more dmac channels are used, the register bank 1 is em ployed as dmac registers. dma2 transfer count register dma3 transfer count register dma2 memory address register dma3 memory address register dma2 sfr address register dma3 sfr address register dma2 transfer count reload register (1) dma3 transfer count reload register (1) when three or more dmac channels are used, the high-speed interrupt regi sters are employed as dmac registers. dct0 dct1 drc0 drc1 dmd0 dmd1 dma2 memory address reload register (1) dma3 memory address reload register (1) dra2(svp) dra3(vct) svf flag save register dma0 dma1 dsa0 dsa1 dra0 dra1 dma2(a0) dma3(a1) dsa2(sb) dsa3(fb) dct2(r0) dct3(r1) drc2(r2) drc3(r3) when using dma2 and dma3, use the cpu registers shown in parentheses ( ). note: 1. these registers are used for repeat transfer, not for single transfer. m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 121 of 352 rej09b0385-0100 a software trigger or an interrupt requ est generated by individual peripheral functions can be the dma transfer request source. bits dsel 4 to dsel0 in the dmisl register determ ine which source is selected. when a software trigger is selected, a dma transfer is started by setting the dsr bit in the dmisl register to 1. when a peripheral function interrupt request is selected, a dma tr ansfer is started by an interrupt request occurrence. the dma transfer is performed even if interrupts are disabl ed by the i flag, ipl, or interrupt co ntrol register, since dmac is free from these affects. when an interrupt request (dma request) is generated, the ir bit in the interrupt control register becomes 1. the ir bit, however, does not beco me 0 even if the dma transfer is performed. table 13.1 dmac specifications item specification number of channels 4 channels (cycle-steal method) transfer memory space from a given address in a 16-mb yte space to a fixed address in a 16-mbyte space from a fixed address in a 16-mbyte space to a given address in a 16-mbyte space maximum bytes transferred 128 kbytes (when a 16-bit data is transferred) 64 kbytes (when an 8-bit data is transferred) dma request source falling edge or both edges of signals applied to pins int0 to int3 timer a0 to a4 interrupt requests timer b0 to b5 interrupt requests uart0 to uart4 transmit and receive interrupt requests a/d0 interrupt request software trigger channel priority dma0 > dma1 > dma2 > dma3 (dma0 has the highest priority) transfer unit 8 bits, 16 bits transfer address fixed addr ess: one specified address incremented address: address which is incremented by a transfer unit on each successive access. (source address and destination address cannot be both fixed nor both incremented.) transfer mode single transfer transfer is completed when the dcti register (i = 0 to 3) becomes 0000h repeat transfer when the dcti register becomes 00 00h, values of the drci register are reloaded into the dcti register and the dma transfer continues. dma interrupt request generation timing when the dcti register becomes from 0001h to 0000h, a dma interrupt request is generated. dma startup single transfer dmac starts a data transfer when a dma request is generated after bits mdi1 and mdi0 in the dmdj register (j = 0 to 1) are set to 01b (single transfer), while the dcti register is set to 0001h or higher value. repeat transfer dmac starts a data transfer when a dma request is generated after bits mdi1 and mdi0 are set to 11b (repeat transfer), while the dcti register is set to 0001h or higher value. dma stop single transfer when bits mdi1 and mdi0 are set to 00b (dma disabled) dmac stops when the dcti register becomes 0000h (0 dma transfer) by a dma transfer completion or by writing. repeat transfer when bits mdi1 and mdi0 are set to 00b (dma disabled) dmac stops when the dcti register becomes 0000h (0 dma transfer) by a dma transfer completion or writing and the drci register is 0000h. reload timing to registers dcti and dmai values are reloaded when the dcti register becomes from 0001h to 0000h in repeat transfer mode. dma transfer time between sfr area and internal ram transfer: minimum 3 bus clock cycles m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 122 of 352 rej09b0385-0100 figure 13.2 dm0sl to dm3sl registers b7 b6 b5 b4 b1 b2 b3 dmai request source select register (i=0 to 3) symbol dm0sl to dm3sl address 0378h, 0379h, 037ah, 037bh bit symbol bit name rw dsel0 after reset 0x00 0000b rw notes: 1. change settings of bits dsel4 to dsel0 while bits md i1 and mdi0 in the dmd0 or dmd1 register are set to 00b (dma disabled). also, when bits dsel4 to d sel0 are change, set the drq bit to 1 at the same time. e.g., mov.b #083h, dmisl ; select timer a0 2. when the dsr bit is set to 1, set the drq bit to 1 at the same time. e.g., or.b #0a0h, dmisl 3. do not write a 0 to the drq bit. b0 function dsel1 software dma request bit (2) when a software trigger is selected, a dma request is generated by setting this bit to 1 (read as 0) reserved bit dma request bit (2, 3) read as undefined value 0: not requested 1: requested rw rw rw ? rw dsel2 dsel3 dsel4 dsr ? (b6) drq dma request source select bits (1) see table "dmisl register function (i = 0 to 3)" do not set to values other than specified in the table. rw rw m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 123 of 352 rej09b0385-0100 table 13.2 dmisl register (i = 0 to 3) function notes: 1. when the int3 pin is used for data bus in microprocessor mode, a dma3 interrupt request cannot be generated by an input signal to the int3 pin. 2. the falling edge or both edges of input signal to the inti pin can be a dma request source. it is not affected by the int interrupts (bits pol and lvs in the intiic register, the ifsr register) and vice versa. 3. to switch between the uartj receive interrupt and ack interrupt (j = 0 to 4), use the iicm bit in the uismr register and iicm 2 bit on the uismr2 register. to use the ack interrupt, set the iicm bit to 1 (i 2 c mode) and the iicm2 bit to 0 (nack/ack interrupt). setting value dma request source b4 b3 b2 b1 b0 dma0 dma1 dma2 dma3 00000 software trigger 00001falling edge of int0 falling edge of int1 falling edge of int2 falling edge of int3 (1) (note 2) 00010both edges of int0 both edges of int1 both edges of int2 both edges of int3 (1) (note 2) 00011 timer a0 interrupt request 00100 timer a1 interrupt request 00101 timer a2 interrupt request 00110 timer a3 interrupt request 00111 timer a4 interrupt request 01000 timer b0 interrupt request 01001 timer b1 interrupt request 01010 timer b2 interrupt request 01011 timer b3 interrupt request 01100 timer b4 interrupt request 01101 timer b5 interrupt request 01110 uart0 transmit interrupt request 01111 uart0 receive interrupt or ack interrupt request (3) 10000 uart1 transmit interrupt request 10001 uart1 receive interrupt or ack interrupt request (3) 10010 uart2 transmit interrupt request 10011 uart2 receive interrupt or ack interrupt request (3) 10100 uart3 transmit interrupt request 10101 uart3 receive interrupt or ack interrupt request (3) 10110 uart4 transmit interrupt request 10111 uart4 receive interrupt or ack interrupt request (3) 11000 a/d0 interrupt request m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 124 of 352 rej09b0385-0100 figure 13.3 dma0 to dma3 regist ers, dsa0 to dsa3 registers b23 symbol dma0 (2) dma1 (2) dma2 (bank1:a0) (3) dma3 (bank1:a1) (4) address (cpu internal register) (cpu internal register) (cpu internal register) (cpu internal register) after reset xxxxxxh xxxxxxh 000000h 000000h b0 function rw dmai memory address r egister (i = 0 to 3) rw set an incremented source address or incremented destination address (1) notes: 1. when the rwk bit (k = 0 to 3) in the dmdj register (j = 0, 1) is set to 0 (fixed address to incremented address), a des tination address is selected. when the rwk bit is set to 1 (increm ented address to fixed address), a source address is selected. 2. use the ldc instruction to set registers dma0 and dma1. 3. to set the dma2 register, set the b flag in the fl g register to 1 (register bank 1) and write to the a0 register. 4. to set the dma3 register, set the b flag to 1 and write to the a1 register. setting range 000000h to ffffffh (16 mbytes) b16 b15 b8 b7 b23 symbol dsa0 (2) dsa1 (2) dsa2 (bank1:sb) (3) dsa3 (bank1:fb) (4) address (cpu internal register) (cpu internal register) (cpu internal register) (cpu internal register) after reset xxxxxxh xxxxxxh 000000h 000000h b0 function rw dmai sfr address regi ster (i = 0 to 3) rw set a fixed source address or fixed destination address (1) notes: 1. when the rwk bit (k = 0 to 3) in the dmdj register (j = 0, 1) is set to 0 (fixed address to incremented address), a sou rce address is selected. when the rwk bit is set to 1 (incremented address to fixed address), a destination address is selected. 2. use the ldc instruction to set registers dsa0 and dsa1. 3. to set the dsa2 register, set the b flag in the flg r egister to 1 (register bank 1) and write to the sb register using the ldc instruction. 4. to set the dsa3 register, set the b flag to 1 and write to the fb register using the ldc instruction. setting range 000000h to ffffffh (16 mbytes) b16 b15 b8 b7 m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 125 of 352 rej09b0385-0100 figure 13.4 dra0 to dra3 registers, dct0 to dct3 registers, drc0 to drc3 registers b23 symbol dra0 dra1 dra2 (svp) (2) dra3 (vct) (3) address (cpu internal register) (cpu internal register) (cpu internal register) (cpu internal register) after reset xxxxxxh xxxxxxh xxxxxxh xxxxxxh b0 function rw dmai memory address reload register (1) (i = 0 to 3) rw set an incremented source address or incremented destination address notes: 1. use the ldc instruction to set registers dra0 to dra3. 2. to set the dra2 register, write to the svp register. 3. to set the dra3 regi ster, write to the vct register. setting range 000000h to ffffffh (16 mbytes) b16 b15 b8 b7 symbol dct0 (2) dct1 (2) dct2 (bank1:r0) (3) dct3 (bank1:r1) (4) address (cpu internal register) (cpu internal register) (cpu internal register) (cpu internal register) after reset xxxxh xxxxh 0000h 0000h function rw dmai transfer count r egister (i = 0 to 3) rw set the number of transfers notes: 1. when the dcti register is set to 0000h, no dat a transfer occurs regardless of a dma request generation. 2. use the ldc instruction to set registers dct0 and dct1. 3. to set the dct2 register, set the b flag in the flg register to 1 (register bank 1) and write to the r0 register. 4. to set the dct3 register, set t he b flag to 1 and write to the r1 register. setting range 0000h to ffffh (1) b15 b0 b8 b7 b15 symbol drc0 (1) drc1 (1) drc2 (bank1:r2) (2) drc3 (bank1:r3) (3) address (cpu internal register) (cpu internal register) (cpu internal register) (cpu internal register) after reset xxxxh xxxxh 0000h 0000h b0 function rw dmai transfer count reload register (i = 0 to 3) rw set the number of transfers notes: 1. use the ldc instruction to set registers drc0 and drc1. 2. to set the drc2 register, set the b flag in the flg register to 1 (register bank 1) and write to the r2 register. 3. to set the drc3 register, set t he b flag to 1 and write to the r3 register. setting range 0000h to ffffh b8 b7 m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 126 of 352 rej09b0385-0100 figure 13.5 dmd0 register b7 b6 b5 b4 b1 b2 b3 dma mode register 0 (1) symbol dmd0 address (cpu internal register) bit symbol rw md00 after reset 00h rw note: 1. use the ldc instruct ion to set the dmd0 register. b0 md01 rw rw bw0 rw0 md10 rw1 rw rw md11 bw1 rw rw rw channel 0 transfer unit select bit channel 1 transfer unit select bit channel 0 transfer mode select bits channel 0 transfer direction select bit channel 1 transfer mode select bits channel 1 transfer direction select bit bit name function 0: 8 bits 1: 16 bits 0: 8 bits 1: 16 bits b1 b0 0 0: dma disabled 0 1: single transfer 1 0: do not set to this value 1 1: repeat transfer 0: fixed address to incremented address 1: incremented address to fixed address b5 b4 0 0: dma disabled 0 1: single transfer 1 0: do not set to this value 1 1: repeat transfer 0: fixed address to incremented address 1: incremented address to fixed address m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 127 of 352 rej09b0385-0100 figure 13.6 dmd1 register dma mode register 1 (1) symbol dmd1 address (cpu internal register) bit symbol rw md20 after reset 00h note: 1. use the ldc instruct ion to set the dmd1 register. md21 bw2 rw2 md30 rw rw rw rw md31 rw bw3 rw rw3 rw rw b7 b6 b5 b4 b1 b2 b3 b0 bit name channel 2 transfer mode select bits channel 3 transfer unit select bit channel 3 transfer direction select bit channel 2 transfer unit select bit channel 2 transfer direction select bit channel 3 transfer mode select bits b1 b0 0 0: dma disabled 0 1: single transfer 1 0: do not set to this value 1 1: repeat transfer 0: 8 bits 1: 16 bits b5 b4 0 0: dma disabled 0 1: single transfer 1 0: do not set to this value 1 1: repeat transfer 0: 8 bits 1: 16 bits 0: fixed address to incremented address 1: incremented address to fixed address 0: fixed address to incremented address 1: incremented address to fixed address function m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 128 of 352 rej09b0385-0100 figure 13.7 register settings when using dma0 or dma1 dmd0 register: bits md01 and md00 = 00b bits md11 and md10 = 00b dma disabled for channel 0 dma disabled for channel 1 write with ldc instruction start i = 0 and 1 notes: 1. when setting the dmisl r egister, write a 1 to the drq b it. 2. when the int interrupts are selected as a dma request s ource, do not write a 1 to the dcti register. if the dcti regi ster is 1, do not generate a dma request when writing 01b or 11b to bit s mdi1 and mdi0. 3. wait six cpu clock cycles o r more by program to set bit s mdi1 and mdi0 to 01b or 11b after setting the dmisl register. 4. when a dma transfer is sta rted by the software trigger, set both the dsr and drq bit in the dmisl register to 1 at the same time. dma request source select bits dma requested set an incremented source address or incremented destination address set a fixed source address or fixed destination address set an incremented source address or incremented destination address set the number of transfers (2) transfer mode select bits for channel 0 transfer unit select bit for channel 0 transfer direction select bit for channel 0 transfer mode select bits for channel 1 transfer unit select bit for channel 1 transfer direction select bit for channel 1 end write with ldc instruction write with ldc instruction (note 1) (note 4) set the number of transfers, which is to be reloaded m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 129 of 352 rej09b0385-0100 figure 13.8 register settings when using dma2 or dma3 write with ldc instruction start dma disabled for channel 2 dma disabled for channel 3 dma request source select bits dma requested transfer mode select bits for channel 2 transfer unit select bit for channel 2 transfer direction select bit for channel 2 transfer mode select bits for channel 3 transfer unit select bit for channel 3 transfer direction select bit for channel 3 end select register bank 1 (2) set an incremented source address or incremented destination address write with mov instruction set a fixed source address or fixed destination address write with ldc instruction dra2 (svp) register or dra3 (vct) register set an incremented source address or incremented destination address set the number of transfer (3) write with mov instruction set the number of transfer, which is to be reloaded write with ldc instruction (note 1) (note 5) i = 2 and 3 notes: 1. when setting the dmisl r egister, write a 1 to the drq b it. 2. the register bank 1 and high-speed interrupt cannot be used when using dma2 and dma3. 3. when the int interrupts ar e selected as a dma request s ource, do not write a 1 to the dcti register. if the dcti regi ster is 1, do not generate a dma request when writing 01b or 11b to bit s mdi1 and mdi0. 4. wait six cpu clock cycles or more by program to set bit s mdi1 and mdi0 to 01b or 11b after setting the dmisl register. 5. when a dma transfer is sta rted by the software trigger, set both the dsr and drq bit in the dmisl register to 1 at the same time. m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 130 of 352 rej09b0385-0100 13.1 transfer cycles the transfer cycle is composed of bus cycles to read da ta from source address (source read) and bus cycles to write data to destination address (destinatio n write). the number of read and wr ite bus cycles depe nds on the locations of source and destination addresses. in microprocessor mo de, the number of read and write bus cycles also depends on ds register setting. software wait state insertion and the rdy signal can extend a bus cycle. 13.1.1 effect of source and destination addresses when a 16-bit data is transferred with a 16-bit data bus and a source address starts with an odd address, the source-read cycle is added by one bus cycle, compared to a source address starting with an even address. when a 16-bit data is transf erred with a 16-bit data bus and a destinati on address starts with an odd address, the destination-write cycle is added by one bus cycle, comp ared to a destination address starting with an even address. 13.1.2 effect of the ds register in an external space in microprocessor mode, the transf er cycle varies depending on the data bus width of the source and destination addresses. see figure 8.1 for details about the ds register. ? when a 16-bit data is transferred accessing both source address and des tination address w ith an 8-bit data bus (the dsi bit in the ds register is set to 0 (i = 0 to 3)), an 8-bit data will be transferred twice. therefore, two bus cycles are required for reading and another two bus cycles for writing. ? when a 16-bit data is transferred acce ssing a source address with an 8-bit data bus (the dsi bit is set to 0) and a destination address with a 16-bit data bus, an 8- bit data will be read twice but be written once as 16- bit data. therefore, two bus cycles are requir ed for reading and one bus cycle for writing. ? when a 16-bit data is transferred acce ssing a source address with a 16-bit data bus (the dsi bit is set to 1) and a destination address with an 8-bit data bus, a 16-bit data will be read once and an 8-bit data will be written twice. therefore, one bus cycle is requ ired for reading and two bus cycles for writing. 13.1.3 effect of soft ware wait state when accessing the sfr area or memory space that require wait states, th e number of bus clocks (bclk) is increased by software wait states. 13.1.4 effect of the rdy signal in microprocessor mode, the rdy signal affects a bus cycle if a source address or destination address is in an external space. refer to 8.2.6 rdy signal for details. m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 131 of 352 rej09b0385-0100 13.2 dma transfer time the dma transfer time can be calculated as follows. (in terms of bus clock) table 13.3 lists the number of the source read cycle and destination write cycle. table 13.4 lists coefficient j, k (the number of bus clock). transfer time = source read bus cycle j + destination write bus cycle k table 13.3 source read cycle and destination write cycle i=0 to 3, p=0 and 1 table 13.4 coefficient j, k 13.3 channel priori ty and dma transfer timing when multiple dma requests are generated in the same sampling period (between a falling edge of the bclk and the next falling edge), the corresponding drq bits in th e dmisl register (i = 0 to 3) are set to 1 (requested) simultaneously. channel priority in this case is: dm a0 > dma1 > dma2 > dma3. leave the following period between each dma transfer reques t generation on the same channel. dma request interval (number of channels set for dma transfer - 1) 5 bclk cycles described in the following is the operation when dma0 and dma1 requests are gene rated in the same sampling period. figure 13.9 shows an example of dma transfers triggered by the int interrupts. in figure 13.9, dma0 and dma1 requests are generated simultaneously. a dma0 request having higher priority is acknowledged first to start a transf er. after one dma0 transfer is comp leted, the dmac returns ownership of the bus to the cpu. when the cpu has completed one bus access, a dma1 transfer starts. after one dma1 transfer is completed, bus ownership is again returned to the cpu. dma requests cannot be counted up since each channel ha s one drq bit. even if multiple dma1 requests are generated before receiving bus ownership as shown in figure 13.9, the drq bit is set to 0 as soon as bus ownership is acquired. bus ownership is returned to the cpu after one transfer is completed. transfer unit bus width access address accessing internal space accessing external space read cycle write cycle read cycle write cycle 8-bit transfer (bwi bit in the dmdp register = 0) 16 bits even 1 1 1 1 odd 1 1 1 1 8 bits even ?? 11 odd ?? 11 16-bit transfer (bwi bit = 1) 16 bits even 1 1 1 1 odd 2 2 2 2 8 bits even ?? 22 odd ?? 22 internal space external space internal ram internal ram sfr area j and k bclk cycles shown in table 8.6 (j, k = 2 to 9). add one cycle to j or k cycles when inserting a recovery cycle with no wait state j=1 k=1 with wait state j=2 k=2 j=2 k=2 m32c/8a group 13. dmac rev.1.00 jul 15, 2007 page 132 of 352 rej09b0385-0100 figure 13.9 dma transfers triggered by int interrupt requests bclk dma0 dma1 cpu int0 int1 drq bit in dma0 drq bit in dma1 example when dma transfer requests for dma0 and dma1 are generated simultaneously and dma transfers (sfr to ram) are performed in minimum time. bus privilege acquired m32c/8a group 14. dmacii rev.1.00 jul 15, 2007 page 133 of 352 rej09b0385-0100 14. dmacii dmacii performs memory-to-memory transfer, immediate data transfer, and calculation transfer which transfers a result of the addition of two data. dmacii transfer occurs in response to interrupt requests from the peripheral functions. table 14.1 lists specifications of dmacii. table 14.1 dmacii specifications notes: 1. when a destination address is 0ffffh and a 16-bit data is transferred, it is transferred to addresses 0ffffh and 10000h. likewise, when a source address is 0ffffh , a 16-bit data in addresses 0ffffh and 10000h is transferred to a given destination address. 2. the actual transferable space varies depending on internal ram capacity. 14.1 dmacii settings set up the following registers and tables to activate dmacii. ? rlvl register ? dmacii index ? interrupt control register of the periphe ral functions triggering dmacii requests ? the relocatable vector table of the periph eral functions triggering dmacii requests 14.1.1 rlvl register when the dmaii bit is set to 1 (interrupt priority le vel 7 is used for dmacii transfer) and the fsit bit to 0 (interrupt priority level 7 is used for normal interrupt), dmacii is activated by an interrupt request from any peripheral functions with bits ilvl2 to ilvl0 in the interrupt control register set to 111b (level 7). figure 14.1 shows the rlvl register. item specification dmacii request source interrupt requests generated by any peripheral functions with bits ilvl2 to ilvl0 in the interrupt control register set to 111b (level 7) transfer data - data in a memory location is transferred to another memory location (memory-to-memory transfer) - immediate data is transferred to a memory location (immediate data transfer) - data in a memory location (or immediate data) + data in another memory location is transferred to the other memory location (calculation transfer) transfer unit 8 bits or 16 bits transfer space 64-kbyte space in addresses 00000h to 0ffffh (1)(2) transfer address fixed addr ess: one specified address incremented address: address which is incremented by the transfer unit on each successive access. (selectable for source address and destination address individually) transfer mode single transfer, burst transfer, multiple transfer chain transfer function address indicated by an interrupt vector for dmacii index is replaced when a transfer counter reaches zero end-of-transfer interrupt interrupt occurs when a transfer counter reaches zero m32c/8a group 14. dmacii rev.1.00 jul 15, 2007 page 134 of 352 rej09b0385-0100 figure 14.1 rlvl register b7 b6 b5 b4 b1 b2 b3 symbol rlvl address 009f after reset xxxx 0000b b0 function bit symbol bit name rw rw exit priority register rw rw rw rw ? rlvl0 exit wait mode/stop mode interrupt priority level control bits (1) rlvl1 rlvl2 b2 b1 b0 0 0 0: level 0 0 0 1: level 1 0 1 0: level 2 0 1 1: level 3 1 0 0: level 4 1 0 1: level 5 1 1 0: level 6 1 1 1: level 7 fsit dmaii high-speed interrupt select bit dmacii select bit (4) 0: interrupt priority level 7 is used for interrupt 1: interrupt priority level 7 is used for dmacii transfer (2) 0: interrupt priority level 7 is used for normal interrupt 1: interrupt priority level 7 is used for high-speed interrupt (2)(3) ? (b7-b6) ? unimplemented. write 0. read as undefined value. notes: 1. the mcu exits stop or wait mode when an interrupt prio rity level of a requested interrupt is higher than a level set us ing bits rlvl2 to rlvl0. set bits rlvl2 to rlvl0 to the same value as ipl in the flg register. 2. do not set both the fsit and dmaii bits to 1. set either the fsit bit or the dmaii bit to 1 befor e setting bits ilvl2 to ilvl0 in th e interrupt control register to 111b. 3. only one interrupt can have the interrupt pr iority level 7 when selecting the high-speed interrupt. 4. the dmaii bit is undefined after reset. to use interrupt priority level 7 for an interrup t, set it to 0 before setting the interrupt control register. ? (b4) unimplemented. write 0. read as undefined value. m32c/8a group 14. dmacii rev.1.00 jul 15, 2007 page 135 of 352 rej09b0385-0100 14.1.2 dmacii index the dmacii index is an 8- to 32-byte data table, which stores parameters for transf er mode, transfer counter, source address (or immediate data), operation address as an address to be calculated, destination address, chain transfer address, and end-of -transfer interrupt address. the dmacii index must be located on the ram area. figure 14.2 shows a configuration of the dmacii index. table 14.2 lists an example configuration of the dmacii index. figure 14.2 dmacii index details of the dmacii index are described below. set these parameters in the spec ified order listed in table 14.2, depending on dmacii transfer mode. ? transfer mode (mod) mod is two-byte data and required to set transfer mode . figure 14.3 shows a configuration for transfer mode. ? transfer counter (count) count is two-byte data and required to set the number of transfer. ? transfer source address (sadr) sadr is two-byte data and required to set a source memory address or immediate data. ? operation address (oadr) oadr is two-byte data and required to set a memory addr ess to be calculated. set this data only when using the calculation transfer function. ? transfer destination address (dadr) dadr is two-byte data and required to set a destination memory address. ? chain transfer address (cadr) cadr is four-byte data and required to set the starting address of the dmacii index for the next transfer. set this data only when using the chain transfer function. ? end-of-transfer interrupt address (iadr) iadr is four-byte data and required to set a jump addre ss for end-of-transfer interrupt processing. set this data only when using the end-of-transfer interrupt. the abbreviations sh own in parentheses( ) for each pa rameter are used in this section. multiple transfer memory-to-memory transfer, immediate transfer, calculation transfer base+8 base+4 base+6 base+2 base+16 base+12 base+14 base+10 transfer mode (mod) transfer destination address (dadr) transfer source address (or immediate data) (sadr) operation address (1) (oadr) transfer counter (count) end-of-transfer interrupt address (higher byte) (3) (iadr1) chain transfer address (higher byte) (2) (cadr1) end-of-transfer interrupt address (lower byte) (3) (iadr0) chain transfer address (lower byte) (2) (cadr0) dmacii index starting address (base) 16 bits notes: 1. this data is not needed unle ss using the calculation transfer function. 2. this data is not needed unle ss using the chain transfer function. 3. this data is not needed unl ess using the end-of-transfer interrupt. base+8 base+4 base+6 base+2 base+30 base+28 base+10 transfer mode (mod) transfer source address (sadr2) transfer source address (sadr1) transfer destination address (dadr1) transfer counter (count) transfer destination address (dadr7) transfer source address (sadr7) transfer destination address (dadr2) base 16 bits place the dmacii index in the ram. necessary data must be set t op-aligned without any space. for example, if not using the calculation transfer function, assign a transfer destination address to base+6. the starting address of the dmacii index must be assigned to the in terrupt vector of the peripheral function interrupt triggeri ng a dmacii request. to m32c/8a group 14. dmacii rev.1.00 jul 15, 2007 page 136 of 352 rej09b0385-0100 table 14.2 dmacii index configuration in transfer mode figure 14.3 mod dmac ii index not used chain transfer used used not used end-of- transfer interrupt not used used not used used transfer data memory-to-memory transfer/ immediate data transfer multiple transfer calculation transfer used cannot used not used not used used used not used used not used 8 bytes 12 bytes 16 bytes 18 bytes mod sadr dadr count mod cadr0 sadr dadr count cadr1 mod iadr0 sadr dadr count iadr1 mod cadr0 sadr dadr count iadr0 iadr1 cadr1 mod dadr sadr oadr count iadr1 cadr1 iadr0 cadr0 mod dadr sadr oadr count mod dadr sadr oadr count cadr1 cadr0 mod dadr sadr oadr count iadr1 iadr0 mod dadr1 sadr1 count dadri sadri 10 bytes 14 bytes 14 bytes i = 1 to 7 max. 32 bytes (when i = 7) cannot used 12 bytes b15 b8 b7 b0 function (mult = 0) bit symbol bit name rw transfer mode (mod) (1) notes: 1. mod must be located in the ram. 2. when the mult bit is set to 0, bits 6 to 4 function as bits oper, brst, and inte. when the mult bit is set to 1, bits 6 to 4 function as bits cnt2 to cnt0. function (mult = 1) size transfer unit select bit 0: 8 bits 1: 16 bits rw imm transfer data select bit 0: immediate data 1: memory rw set to 1 upds transfer source direction select bit 0: fixed address 1: incremented address rw updd transfer destination direction select bit 0: fixed address 1: incremented address rw calculation transfer function select bit 0: not used 1: used rw b6 b5 b4 0 0 0: do not set to this value 0 0 1: once 0 1 0: twice : : 1 1 0: 6 times 1 1 1: 7 times oper/ cnt0 (2) burst transfer select bit 0: single transfer 1: burst transfer rw brst/ cnt1 (2) end-of-transfer interrupt select bit 0: interrupt not used 1: interrupt used rw inte/ cnt2 (2) chain chain transfer select bit 0: chain transfer not used 1: chain transfer used rw set to 0 ? (b14-b8) unimplemented. write 0. read as undefined value. ? mult multiple transfer select bit 0: multiple transfer not used rw 1: multiple transfer used m32c/8a group 14. dmacii rev.1.00 jul 15, 2007 page 137 of 352 rej09b0385-0100 14.1.3 interrupt control regist er for the peripheral function to use the peripheral function interrupt as a dmacii request source, set bits ilvl2 to ilvl0 to 111b (level 7). 14.1.4 relocatable vector tabl e for the peripheral function set the starting address of the dmacii index in an interrupt vector for the peripheral function interrupt used as a dmacii request source. when using the chain transfer, the relocatable vector table must be located in the ram. 14.2 dmacii performance the dmacii function is selected by setting the dmaii bi t to 1 (interrupt priority level 7 is used for dmacii transfer). dmacii transfer request is generated by interrupt requests from an y peripheral function with bits ilvl2 to ilvl0 set to 111b (level 7). these peripheral functi on interrupt requests are used as dmacii transfer requests and the peripheral function interrupts cannot be used. when an interrupt request with bits ilvl2 to ilvl0 se t to 111b (level 7) is gene rated, dmacii is activated regardless of the i flag and ipl settings. 14.3 transfer data dmacii transfers data in 8-bit unit or 16-bit unit. ? memory-to-memory transfer: data is transferred fr om a given memory location in the 64-kbyte space (addresses 00000h to 0ffffh) to another given memory location in the same space. ? immediate data transfer: immediate data is transfer red to a given memory lo cation in the 64-kbyte space. ? calculation transfer: two 8-bit or two 16-bit data are added together and th e result is transferred to a given memory location in the 64-kbyte space. when a 16-bit data is transferred to a destination addr ess 0ffffh, it is tr ansferred to addresses 0ffffh and 10000h. likewise, when a source address is 0ffffh, a 16-b it data in addresses 0ffffh and 10000h is transferred to a given destination address. the actual transferable space varies depend ing on internal ram capacity. refer to figure 3.1 for the internal memory. 14.3.1 memory-to-memory transfer data transfer between any two memory locations in the 64-kbyte space can be: ? a transfer from a fixed address to another fixed address; ? a transfer from a fi xed address to an incremented address; ? a transfer from an incremente d address to a fixed address; ? a transfer from an incremented addr ess to another incremented address. when an incremented address is select ed, dmacii increments an address after every tran sfer for the following transfer. in a 8-bit data transfer, a transfer address is incremented by one. in a 16-bit data transfer, a transfer address is incremented by two. when a source or destination addres s exceeds 0ffffh as a result of a ddress incrementation, the source or destination address returns to 00000h and continues incr ementation. maintain sour ce and destination address at 0ffffh or below. m32c/8a group 14. dmacii rev.1.00 jul 15, 2007 page 138 of 352 rej09b0385-0100 14.3.2 immediate data transfer dmacii transfers immediate data to a given memory location. a fixed or incremented address can be selected as a destination address. store immedi ate data into sadr. to transfer an 8- bit immediate data, write data in the low-order byte of sadr. (the high-order byte is ignored.) 14.3.3 calculation transfer after two memory data, or an immediate data and a memory data, are added together, dmacii transfers the calculated result to a given memory location. set a memory address or immediate data to be calculated in sadr. set another memory address to be calculat ed in oadr. to use a ?memory + memory? calculation transfer, a fixed or incremen ted address can be selected as a source or destination address. if a source address is incremented, an operation address also becomes incr emented. to use an ?immediate data + memory? calculation transfer, a fixed or incremented addr ess can be selected as a destination address. 14.4 transfer modes in dmacii, a single transfer, burst tr ansfer, and multiple tran sfer are available. the brst bit in mod selects either a single transfer or burst transfer, and the mult bit in mod selects a multiple transfer. count determines how many transfers occur. no transfer occurs when count is set to 0000h. 14.4.1 single transfer for one transfer request, dmacii transfers an 8-bit or 16-bit data once. when an incremented address is selected for a source or destination address, dmacii increments the address after every transfer for the following transfer. count is decremented every time a tr ansfer occurs. if using the end-of-transfer interrupt, an interrupt occurs when count reaches zero. 14.4.2 burst transfer for one transfer request, dmacii co ntinuously transfers data the number of times determined by count. count is decremented every time dmacii transfers one transfer unit, and when it reaches zero, a burst transfer is completed. if using the end-of-transfer interrup t, an interrupt occurs at th e end of the burst transfer. while the burst transfer is taking pl ace, no interrupt can be acknowledged. 14.4.3 multiple transfer when using the multiple transfer, select the memory-t o-memory transfer. for one transfer request, dmacii transfers data multiple times. bits cnt2 to cnt0 in mod selects the number of transfers from 001b (once) to 111b (7 times). do not set bits cnt2 to cnt0 to 000b. source and destination addresses enough for all transfers must be allocate d alternately in addresses following mod and count in dmacii index. while the transfers are taking place the number of times set using bits cnt2 to cnt0, no interrupt can be acknowledged. when the multiple transfer is selected, a calculation transfer, burst transfer, chain transfer, and end-of-transfer interrupt cannot be used. m32c/8a group 14. dmacii rev.1.00 jul 15, 2007 page 139 of 352 rej09b0385-0100 14.5 chain transfer the chain transfer can be select ed with the chain bit in mod. the chain transfer is performed as follows. (1) transfer occurs in response to an interrupt request from a peripheral function and is performed according to the contents of the dmacii index at the address specifi ed by the interrupt vector . for one transfer request, either a single transfer or burst transfer selected by the brst bit in mod occurs. (2) when count reaches zero, the interr upt vector in (1) is replaced with the address written in cadr1 and cadr0. the end-of-transfer interrupt occurs after the replacement, if the inte bit in mod is set to 1. (3) when the next dmacii transfer request is generated, the transfer is performed according to the contents of the dmacii index specified by the interrupt vector whic h has been replaced in (2). figure 14.4 shows the relocatab le vector and dmacii index wh en using the chain transfer. for the chain transfer, the relocatable v ector table must be located in the ram. figure 14.4 relocatable vector and dmacii index when using the chain transfer 14.6 end-of-transfer interrupt the end-of-transfer interrupt can be se lected with the inte bit in mod. set the starting address of the end-of- transfer interrupt routine in iadr1 and iadr0. the end-of-transfer interr upt occurs when count reaches zero. base (a) dmacii index (b) intb dmacii index (a) (cadr1, cadr0) base (b) (cadr1, cadr0) relocatable vector ram interrupt vector of the peripheral function triggering dmacii request. default value is base (a). base (c) base (b) when count reaches zero, the above interrupt vector is replaced with base (b), which is the address written in cadr1 and cadr0. when the next request occurs, a transfer starts according to the contents of the dmacii index at base (b). when count reaches zero, the interrupt vector is replaced wtih base (c). m32c/8a group 14. dmacii rev.1.00 jul 15, 2007 page 140 of 352 rej09b0385-0100 14.7 execution time dmacii execution time is calculated by the following equations (single-speed mode): multiple transfers: t [bus clock] = 21+ (11 + b + c) k other than multiple transfers: t [bus clock] = 6 + (26 + a + b + c + d) m + (4 + e) n a: if imm = 0 (source is immediate da ta), a = 0; if imm = 1 (source is data in memory location), a = -1. b: if upds = 1 (source address is incremented), b = 0; if upds = 0 (source address is fixed), b = 1. c: if updd = 1 (destination address is incremented), c = 0; if updd = 0 (destination address is fixed), c = 1. d: if oper = 0 (calculation function is not selected), d = 0; if oper = 1 (calculation function is selected) and upds = 0 (source is immediate data or fixed address in memory location), d = 7; if oper = 1 (calculation function is selected) and upds = 1 (source is incr emented address in memory location), d = 8. e: if chain = 0 (chain transfer is not selected), e = 0; if chain = 1 (chain transfer is selected), e = 4. m: if brst = 0 (single tr ansfer), m = 1; if brst = 1 (burst transfer), m = a value set in count. n: if count = 1, n = 0; if count = 2 or more, n = 1. k: the number of transfers set in bits cnt2 to cnt0 in mod. the above equations are approximations. the execution time varies depending on cpu state, bus wait states, and dmacii index allocation. the first instruction of the end-of-tra nsfer interrupt routine is executed in the eighth bus clock after the dmacii transfer is completed. figure 14.5 transfer time when a dmacii transfer request is generated simultaneously with another request having a higher priority (e.g., nmi or watchdog timer), the interrupt with higher priority is acknowledged first, and the pending dmacii transfer starts after the interrupt sequence of the hi gher priority interrupt has been completed. conditions of the example below: -memory-to-memory transfer (a = -1) -incremented source address (b = 0) -fixed destination address (c = 1) -no calculation function (d = 0) -no chain transfer (e = 0) -single transfer (m = 1) -the end-of-transfer interrupt (transfer counter = 2) occurs transfer counter = 2 transfer counter is decremented. transfer counter = 1 7 clocks dmacii transfer requested program first dmacii transfer t = 6 + 26 x 1 + 4 x 1 = 36 bus clocks second dmacii transfer t = 6 + 26 x 1 + 4 x 0 = 32 bus clocks dmacii transfer requested first dmacii transfer end-of-transfer interrupt routine executed 32 clocks program transfer counter = 1 transfer counter is decremented. transfer counter = 0 second dmacii transfer 36 clocks m32c/8a group 15. timers rev.1.00 jul 15, 2007 page 141 of 352 rej09b0385-0100 15. timers the m32c/8a group has eleven 16-bit timers, and they are separated into five timer a and six timer b based on their functions. individual timers function independently. the count source for each timer is used to operate the timer for counting and reloading, etc. figures 15.1 and 15.2 show block diagrams of timer a and timer b configurations. figure 15.1 timer a configuration timer a3 xcin clock prescaler 1/32 set the cpsr bit in the cpsrf register to 1 reset tck1 and tck0, tmod1 and tmod0: bits in the taimr register taigh, taigl: bits in the onsf register or the trgsr register (i = 0 to 4) fc32 timer a0 timer a1 timer a2 timer a4 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 tck1 and tck0 f1 f8 f2n fc32 ta0in ta1in ta2in ta3in ta4in 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 tck1 and tck0 tck1 and tck0 tck1 and tck0 tck1 and tck0 timer b2 overflow or underflow signal tmod1 and tmod0 00: timer mode 10: one-shot timer mode 11: pwm mode 01: event counter mode 00: timer mode 10: one-shot timer mode 11: pwm mode 01: event counter mode 00: timer mode 10: one-shot timer mode 11: pwm mode 01: event counter mode 00: timer mode 10: one-shot timer mode 11: pwm mode 01: event counter mode 00: timer mode 10: one-shot timer mode 11: pwm mode 01: event counter mode ta0tgh and ta0tgl tmod1 and tmod0 ta1tgh and ta1tgl tmod1 and tmod0 ta3tgh and ta3tgl tmod1 and tmod0 ta4tgh and ta4tgl tmod1 and tmod0 ta2tgh and ta2tgl noise filter noise filter noise filter noise filter noise filter m32c/8a group 15. timers rev.1.00 jul 15, 2007 page 142 of 352 rej09b0385-0100 figure 15.2 timer b configuration timer b0 timer b0 interrupt timer b1 interrupt timer b2 interrupt f1 f8 f2n fc32 tb0in tb1in tb2in tck1 and tck0, tmod1 and tmod0: bits in the tbimr register (i = 0 to 5) timer b1 timer b2 timer b3 timer b3 interrupt timer b4 interrupt timer b5 interrupt tb3in tb4in tb5in tck1 tck1 and tck0 tck1 timer b5 00 01 10 11 tck1 and tck0 0 1 tck1 timer b2 overflow or underflow signal (to the count source of timer a) noise filter 00 01 10 11 0 1 noise filter timer b4 tck1 and tck0 00 01 10 11 0 1 noise filter tck1 tck1 and tck0 00 01 10 11 0 1 noise filter tck1 tck1 and tck0 00 01 10 11 0 1 noise filter tck1 tck1 and tck0 00 01 10 11 0 1 noise filter xcin clock prescaler 1/32 set the cpsr bit in the cpsrf register to 1 reset fc32 00: timer mode 10: pulse width measurement mode, pulse cycle measurement mode 01: event counter mode tmod1 and tmod0 00: timer mode 10: pulse width measurement mode, pulse cycle measurement mode 01: event counter mode tmod1 and tmod0 00: timer mode 10: pulse width measurement mode, pulse cycle measurement mode 01: event counter mode tmod1 and tmod0 00: timer mode 10: pulse width measurement mode, pulse cycle measurement mode 01: event counter mode tmod1 and tmod0 00: timer mode 10: pulse width measurement mode, pulse cycle measurement mode 01: event counter mode tmod1 and tmod0 00: timer mode 10: pulse width measurement mode, pulse cycle measurement mode 01: event counter mode tmod1 and tmod0 m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 143 of 352 rej09b0385-0100 15.1 timer a timer a contains the following four modes. except in event counter mode, all timers a0 to a4 have the same functionality. bits tmod1 and tmod0 in the taimr regi ster (i = 0 to 4) determine which mode is used. ? timer mode: the timer counts the internal count source. ? event counter mode: the timer counts overflow/underflow signal of another timer or the external pulses. ? one-shot timer mode: the timer operates only once for one trigger. ? pulse width modulation mode: the timer continuously outputs given pulse widths. figure 15.3 shows a block diagram of timer a. figures 15.4 to 15.13 show the registers associated with timer a. table 15.1 lists taiout pin settings to use in output mode. table 15.2 lists taiin and taiout pin settings to use in input mode. figure 15.3 timer a block diagram reload register 00 01 10 11 clock source select clock select tais polarity selector high-order bits of data bus 8 low-order bits 8 high-order bits increment/decrement taiud toggle flip flop mr2 tmod1 and tmod0 decrement function select register taiout taiin taitgh to taitgl event counter mode timer mode (gate function) timer mode one-shot timer mode pulse width modulation mode tmod1 and tmod0, mr2 tck1 and tck0 tb2 overflow (2) taj overflow (2) tak overflow (2) i = 0 to 4 j = i - 1, except j = 4 if i = 0 k = i + 1, except k = 0 if i = 4 notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. overflow signal or underflow signal. tck1 and tck0, tmod1 and tmoc0, mr2 and mr1: bits in the taimr register taitgh to taitgl: bits in the onsf register if i = 0 or bits in the trgsr register if i = 1 to 4 tais: bit in the tabsr register taiud: bit in the udf register f1 f8 f2n (1) fc32 00 01 10 11 0 1 counter 11 00 01 10 11 low-order bits of data bus tai addresses taj tak timer a0 0347h 0346h timer a4 timer a1 timer a1 0349h 0348h timer a0 timer a2 timer a2 034bh 034ah timer a1 timer a3 timer a3 034dh 034ch timer a2 timer a4 timer a4 034fh 034eh timer a3 timer a0 always decrement except in event counter mode m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 144 of 352 rej09b0385-0100 figure 15.4 tcspr register b7 b6 b5 b4 b1 b2 b3 symbol tcspr address 035fh after reset (2) 0xxx 0000b b0 function bit symbol bit name rw rw cnt3 count source prescaler register cnt1 rw rw cnt2 cnt0 rw ? (b6-b4) ? rw cst if the setting value is n , f2n is the main clock, on-chip oscillator, or pll clock divided by 2n . no division if n = 0 divide ratio select bits (1) read as undefined value 0: divider stops 1: divider stars operation enable bit notes: 1. set the cst bit to 0 before bits cnt3 to cnt0 are rewritten. 2. the tcspr register maintains values set before reset, even after software reset or watchdog timer reset has been perfor med. reserved bits m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 145 of 352 rej09b0385-0100 figure 15.5 ta0mr to ta4mr registers in timer mode b7 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol ta0mr to ta4mr address 0356h, 0357h, 0358h, 0359h, 035ah after reset 00h b0 function bit symbol bit name rw mr3 tck1 gate function select bits rw rw rw rw mr2 rw mr1 count source select bits tck0 timer ai mode register (i = 0 to 4)(timer mode) tmod1 rw reserved bit rw ? (b2) b1 b0 0 0: timer mode operating mode select bits tmod0 rw set to 0 b4 b3 0 0: gate function disabled 0 1: (taiin pin is a programmable i/o port) 1 0: timer counts only while an "l" signal is input to the taiin pin 1 1: timer counts only while an "h" signal is input to the taiin pin set to 0 in timer mode b7 b6 0 0: f1 0 1: f8 1 0: f2n (1) 1 1: fc32 note: 1. bits cnt3 to cnt0 in the tcspr register select no divi sion (n = 0) or divided-by-2n (n = 1 to 15). to select f2n, set the cst bit in the tcspr register to 1 before setting bits tck1 and tck0 to 10b. m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 146 of 352 rej09b0385-0100 figure 15.6 ta0mr to ta4mr registers in event counter mode b7 1 0 0 0 b6 b5 b4 b1 b2 b3 symbol ta0mr to ta4mr address 0356h, 0357h, 0358h, 0359h, 035ah after reset 00h b0 function (when not processing two-phase pulse signals) bit symbol bit name rw mr3 tck1 count polarity select bit (2) rw rw rw rw mr2 rw mr1 tck0 timer ai mode regist er (i = 0 to 4)(e vent counter mode) tmod1 rw reserved bit rw ? (b2) b1 b0 0 1: event counter mode (1) operating mode select bits tmod0 rw set to 0 increment/decrement switching source select bit notes: 1. bits taitgh and taitgl in the onsf or trgs r register determine a count s ource in event counter mode. 2. the mr1 bit is enabled only when counting external signals. 3. the counter decrements when an "l" signal is applied to the taiout pin. the counter in crements when an "h" signal is ap plied to the taiout pin. 4. the tck1 bit is enabled only in the ta3mr register. the tck1 bit in registers ta0mr to ta2mr and ta4mr are disabled. 5. for two-phase pulse signal processing, set the tajp bi t in the udf register (j = 2 to 4) to 1 (two-phase pulse signal p rocessing function enabled). also, set bits tajtgh and tajtgl in the trgsr register to 00b (input to the tajin pin). function (when processing two-phase pulse signals) 0: falling edges of an external signal counted 1: rising edges of an external signal counted set to 0 set to 1 0: udf registser setting 1: signal applied to the taiout pin (3) count operation type select bit two-phase pulse signal processing operation select bit (4,5) 0: normal processing operation 1: multiply-by-4 processing operation set to 0 in event counter mode 0: reload 1: free running set to 0 m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 147 of 352 rej09b0385-0100 figure 15.7 ta0mr to ta4mr registers in one-shot timer mode b7 b6 0 0: f1 0 1: f8 1 0: f2n (2) 1 1: fc32 0: the taios bit enabled 1: selected by bits taitgh and taitgl 0: falling edge of signal applied to the taiin pin 1: rising edge of signal applied to the taiin pin set to 0 b1 b0 1 0: one-shot timer mode b7 0 1 0 0 b6 b5 b4 b1 b2 b3 symbol ta0mr to ta4mr address 0356h, 0357h, 0358h, 0359h, 035ah after reset 00h b0 function bit symbol bit name rw mr3 tck1 rw rw rw rw mr2 rw mr1 count source select bits tck0 timer ai mode regist er (i = 0 to 4)(o ne-shot timer mode) tmod1 rw reserved bit rw ? (b2) operating mode select bits tmod0 rw set to 0 in one-shot timer mode external trigger select bit (1) trigger select bit notes: 1. the mr1 bit is enabled only when bits taitgh and taitgl in the onsf or trgsr register are set to 00b (input to the taii n pin). the mr1 bit can be set to either 0 or 1 when bits taitgh and taitgl are set to 01b (tb2 overflow or underflow), 10b (taj (j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (tak (k = i + 1, except i = 4 if k = 0) overflow or underflow ). 2. bits cnt3 to cnt0 in the tcspr register select no divisi on (n = 0) or divide-by-2n (n = 1 to 15). to select f2n, set t he cst bit in the tcspr register to 1 before setting bits tck1 and tck0 to 10b. m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 148 of 352 rej09b0385-0100 figure 15.8 ta0mr to ta4mr registers in pulse width modulation mode b7 b6 0 0: f1 0 1: f8 1 0: f2n (2) 1 1: fc32 set to 0 b7 1 1 0 b6 b5 b4 b1 b2 b3 symbol ta0mr to ta4mr address 0356h, 0357h, 0358h, 0359h, 035ah after reset 00h b0 function bit symbol bit name rw mr3 tck1 rw rw rw rw mr2 rw mr1 count source select bits tck0 timer ai mode register (i = 0 to 4)(pulse width modulation mode) tmod1 rw reserved bit rw ? (b2) b1 b0 1 1: pulse width modulation (pwm) mode operating mode select bits tmod0 rw 0: falling edge of signal applied to the taiin pin 1: rising edge of signal applied to the taiin pin external trigger select bit (1) 0: the tais bit is enabled 1: selected by bits taitgh and taitgl trigger select bit 0: functions as 16-bit pulse width modulator 1: functions as 8-bit pulse width modulator 16/8-bit pwm mode select bit notes: 1. the mr1 bit is enabled only when bits taitgh and taitgl in the onsf or trgsr register are set to 00b (input to the taii n pin). the mr1 bit can be set to either 0 or 1 when bits taitgh and taitgl are set to 01b (tb2 overflow or underflow), 10b (taj (j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (tak (k = i + 1, except i = 4 if k = 0) overflow or underflow ). 2. bits cnt3 to cnt0 in the tcspr register select no divisi on (n = 0) or divide-by-2n (n = 1 to 15). to select f2n, set t he cst bit in the tcspr register to 1 before setting bits tck1 and tck0 to 10b. m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 149 of 352 rej09b0385-0100 figure 15.9 ta0 to ta4 registers b15 b8 b7 symbol ta0 to ta2 ta3, ta4 address 0347h - 0346h, 0349h - 0348h, 034bh - 034ah 034dh - 034ch, 034fh - 034eh after reset undefined undefined b0 setting range mode function rw timer ai register (1) (i = 0 to 4) rw 0000h to ffffh if a count source frequency is fj and the setting value of tai register is n, the counter cycle is (n + 1) / fj timer mode rw 0000h to ffffh if the setting value is n, the count times are (ffffh - n+1) when the counter increments, and (n+1) when the counter decrements (2) event counter mode wo 0000h to ffffh (3, 4) if the setting value is n, the counter counts n times and stops. one-shot timer mode pulse width modulation mode (16-bit pwm) pulse width modulation mode (8-bit pwm) if a count source frequency is fj and the setting value of the tai register is n, pwm cycle: (2 16 - 1) / fj "h" width of pwm pulse: n / fj if a count source frequency is fj, the setting value of high-order bits in the tai register is n, and the setting value of low-order bits in the tai register is m, pwm cycle: (2 8 -1) x (m+1) / fj "h" width of pwm pulse: (m+1) n / fj 00h to feh (3, 6) (high-order address bits) 00h to ffh (3, 6) (low-order address bits) 0000h to fffeh (3, 5) wo wo fj: f1, f8, f2n, fc32 notes: 1. read and write this register in 16-bit units. 2. the tai register counts external pulses or another timer overflows or underflows. 3. read-modify-write instructions cannot be used to set the tai register. refer to usage notes for details. 4. when the tai register is set to 0000h, the counter does not start and a timer ai interrupt request is not generated. 5. when the tai register is set to 0000h, the pulse width modulator does not operate and the taiout pin output is held "l" . a timer ai interrupt request is not generated. when the tai register is set to ffffh, the pulse width modulator does not operate and the taiout pin output is held "h". a timer ai interrupt request is not generated. 6. when 8 high-order bits are set to 00h, the pulse width modulator does not operate and the taiout pin output is held "l" . a timer ai interrupt request is not generated. when 8 high-order bits are set to ffh, the pulse width modulator does not operate and the taiout pin output is held "h". a timer ai interrupt request is not generated. m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 150 of 352 rej09b0385-0100 figure 15.10 udf register b7 b6 b5 b4 b1 b2 b3 symbol udf address 0344h after reset 00h b0 function bit symbol bit name rw ta2p timer a3 up/down select bit (2) rw rw ta4ud wo ta3ud timer a2 two-phase pulse signal processing function select bit (3) up/down select register (1) timer a4 up/down select bit (2) timer a1 up/down select bit (2) ta1ud rw timer a2 up/down select bit (2) rw ta2ud 0: decrement 1: increment timer a0 up/down select bit (2) ta0ud rw 0: decrement 1: increment 0: decrement 1: increment 0: decrement 1: increment 0: decrement 1: increment 0: two-phase pulse signal processing function disabled 1: two-phase pulse signal processing function enabled notes: 1. read-modify-write instructions c annot be used to set the udf register. refer to usage notes for details. 2. this bit is enabled when the mr2 bit in the taimr register (i = 0 to 4) is set to 0 (the udf register causes increment/ decrement switching) in event counter mode. 3. set these bits to 0 when not us ing the two-phase pulse signal processing function. ta3p wo timer a3 two-phase pulse signal processing function select bit (3) 0: two-phase pulse signal processing function disabled 1: two-phase pulse signal processing function enabled ta4p wo timer a4 two-phase pulse signal processing function select bit (3) 0: two-phase pulse signal processing function disabled 1: two-phase pulse signal processing function enabled m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 151 of 352 rej09b0385-0100 figure 15.11 trgsr register b7 b6 b5 b4 b1 b2 b3 symbol trgsr address 0343h after reset 00h b0 function bit symbol bit name rw rw rw rw rw rw trigger select register rw rw rw note: 1. overflow or underflow. ta1tgh ta2tgh ta3tgl ta2tgl ta1tgl ta3tgh ta4tgl ta4tgh b1 b0 0 0: input to the ta1in pin selected 0 1: tb2 overflows selected (1) 1 0: ta0 overflows selected (1) 1 1: ta2 overflows selected (1) b3 b2 0 0: input to the ta2in pin selected 0 1: tb2 overflows selected (1) 1 0: ta1 overflows selected (1) 1 1: ta3 overflows selected (1) timer a2 trigger select bits b5 b4 0 0: input to the ta3in pin selected 0 1: tb2 overflows selected (1) 1 0: ta2 overflows selected (1) 1 1: ta4 overflows selected (1) timer a3 trigger select bits b7 b6 0 0: input to the ta4in pin selected 0 1: tb2 overflows selected (1) 1 0: ta3 overflows selected (1) 1 1: ta0 overflows selected (1) timer a4 trigger select bits timer a1 trigger select bits m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 152 of 352 rej09b0385-0100 figure 15.12 tabsr register b7 b6 b5 b4 b1 b2 b3 symbol tabsr address 0340h after reset 00h b0 function bit symbol bit name rw tb0s tb2s timer a3 count start bit timer b2 count start bit rw rw rw rw ta4s rw ta3s timer b0 count start bit timer b1 count start bit tb1s count start register timer a4 count start bit timer a1 count start bit ta1s rw timer a2 count start bit rw ta2s 0: count stops 1: count starts timer a0 count start bit ta0s rw 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 153 of 352 rej09b0385-0100 figure 15.13 onsf register b7 b6 0 0: input to the ta0in pin selected 0 1: tb2 overflows selected (2) 1 0: ta4 overflows selected (2) 1 1: ta1 overflows selected (2) 0: z-phase input disabled 1: z-phase input enabled 0: in an idle state 1: timer starts 0: in an idle state 1: timer starts 0: in an idle state 1: timer starts 0: in an idle state 1: timer starts b7 b6 b5 b4 b1 b2 b3 symbol onsf address 0342h after reset 00h b0 function bit symbol bit name rw tazie ta0tgh timer a3 one-shot start bit (1) rw rw rw rw ta4os rw ta3os z-phase input enable bit timer a0 trigger select bits ta0tgl one-shot start register timer a4 one-shot start bit (1) timer a1 one-shot start bit (1) ta1os rw timer a2 one-shot start bit (1) rw ta2os 0: in an idle state 1: timer starts timer a0 one-shot start bit (1) ta0os rw notes: 1. read as 0. 2. overflow or underflow. m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 154 of 352 rej09b0385-0100 table 15.1 taiout pin settings in output mode (i = 0 to 4) notes: 1. set registers ps1and ps2 after setting registers psc, psl1, and psl2. 2. p7_0 is an n-channel open drain output port. table 15.2 taiin and taiout pin settings in input mode (i = 0 to 4) pin function bit setting psc register psl1, psl2 registers ps1, ps2 registers (1) p7_0 (2) ta0out ? psl1_0 = 1 ps1_0 = 1 p7_2 ta1out ? psl1_2 = 1 ps1_2 = 1 p7_4 ta2out psc_4 = 0 psl1_4 = 0 ps1_4 = 1 p7_6 ta3out ? psl1_6 = 1 ps1_6 = 1 p8_0 ta4out ? psl2_0 = 0 ps2_0 = 1 pin function bit setting pd7, pd8 registers ps1, ps2 registers p7_0 ta0out pd7_0 = 0 ps1_0 = 0 p7_1 ta0in pd7_1 = 0 ps1_1 = 0 p7_2 ta1out pd7_2 = 0 ps1_2 = 0 p7_3 ta1in pd7_3 = 0 ps1_3 = 0 p7_4 ta2out pd7_4 = 0 ps1_4 = 0 p7_5 ta2in pd7_5 = 0 ps1_5 = 0 p7_6 ta3out pd7_6 = 0 ps1_6 = 0 p7_7 ta3in pd7_7 = 0 ps1_7 = 0 p8_0 ta4out pd8_0 = 0 ps2_0 = 0 p8_1 ta4in pd8_1 = 0 ps2_1 = 0 m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 155 of 352 rej09b0385-0100 15.1.1 timer mode in timer mode, the timer counts an internally generated count source. table 15.3 lists specifications of timer mode. fi gure 15.14 shows a timer mode operation (timer a). table 15.3 specifications of timer mode notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. wait for one count source cycle or mo re to write after the count starts. figure 15.14 operation in timer mode (timer a) item specification count source f1, f8, f2n (1) , fc32 count operation ? counter decrements when the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. counter cycle n + 1 fj: count source frequency fj n: setting value of the tai register (i = 0 to 4), 0000h to ffffh count start condition the tais bit in the tabsr register is set to 1 (count starts) count stop condition the tais bit is set to 0 (count stops) interrupt request generation timing when the timer underflows taiin pin function input for gate function taiout pin function pulse output read from timer a read from the tai register returns a counter value write to timer ? a write to the tai register while the count is stopped: the value is written to both the reload register and the counter. ? a write to the tai register while counting: the value is written to the reload register (it is transferred to the counter at the next reload timing). (2) selectable function ? gate function a signal applied to the taiin pin determines whether the count starts or stops. ? pulse output function the polarity of the taiout pin is inverted whenever the timer underflows. the taiout pin outputs an ?l? signal while the tais bit is 0 (count stops). count starts ffffh n count stops i = 0 to 4 tais bit in the tabsr register contents of the counter n = contents of the reload register 0000h ir bit in the taiic register 0 1 taiout pin (output) (conditions) taimr register: bit s tmod1 and tmod0 are set to 00 b (timer mode). bits mr2 and mr1 are set to 00b (gate function disabled). underflow reload underflow reload 0 1 l h set to 0 by an interrupt request a cknowledgement or by program m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 156 of 352 rej09b0385-0100 15.1.2 event counter mode in event counter mode, the timer coun ts overflows/underflows of another timer, or the external pulse input. timers a2, a3, and a4 can count exte rnally generated two-phase signals. table 15.4 lists specifications of event counter m ode when not handling two-phase pulse signals. table 15.5 lists specifications of event counter mode when handling two-phase pulse signals with timers a2, a3, and a4. figure 15.15 shows a event counter mode operation when not handling two-phase pulse signals. figure 15.16 shows a event counter mode operation when handling two-phase pulse signals with timers a2, a3, and a4. table 15.4 specifications of event counter mode when not handling two-phase pulse signals note: 1. wait for one count source cycle or mo re to write after the count starts. item specification count source ? external signal applied to the taiin pin (i = 0 to 4) (valid edge is selectable by program) ? timer b2 overflows or underflows ? timer aj overflows or underflows (j = i - 1, except j = 4 if i = 0) ? timer ak overflows or underflows (k = i + 1 except k = 0 if i = 4) count operation ? count direction (increment or decrement) can be selected by external signal or by program. ? reload/free-run type can be selected. reload function: the contents of the reload register are reloaded into the counter and the count continues when the timer underflows or overflows. free-running function: the counter continues running without reloading when the timer underflows or overflows. number of counting (ffffh - n + 1): when incrementing n + 1: when decrementing n: setting value of the tai register, 0000h to ffffh count start condition the tais bit in the tabsr register is set to 1 (count starts) count stop condition the tais bit is set to 0 (count stops) interrupt request generation timing when the timer overflows or underflows taiin pin function count source input taiout pin function pulse output, or input to select the count direction read from timer a read from the tai register returns a counter value write to timer ? a write to the tai register while the count is stopped: the value is written to both the reload register and the counter. ? a write to the tai register while counting: the value is written to the reload register (it is transferred to the counter at the next reload timing). (1) selectable function pulse output function the polarity of the taiout pin is inverted whenever the timer overflows or underflows. the taiout pin outputs ?l? signal while the tais bit is 0 (count stops). m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 157 of 352 rej09b0385-0100 figure 15.15 operation in event counter mode when not handling two-phase pulse signals count starts ffffh n count stops i = 0 to 4 tais bit in the tabsr register contents of the counter n = contents of the reload register 0000h ir bit in the taiic register 0 1 input to taiin pin (conditions) taimr register: bi ts tmod1 and tmod0 are set to 01 b (event counter mode) the mr1 bit is set to 1 (rising edges of an external signal cou nted) the mr2 bit is set to 0 (udf register setting) bits tck1 to tck0 bit are set to 00b (reload) underflow reload overflow reload 0 1 l h set to 0 by an interrupt request acknowledgement or by program decrement to increment count resumes taiud bit in the udf register 0 1 set to 1 by program m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 158 of 352 rej09b0385-0100 table 15.5 specifications of event counter mode when handling two-phase pulse signals on timers a2, a3, and a4 notes: 1. wait for one count source cycle or mo re to write after the count starts. 2. any operation can be selected for timer a3. timer a2 is used only for the normal processing operation. timer a4 is used only for the multiply-by-4 operation. item specification count source two-phase pulse signals applied to pins taiin and taiout (i = 2 to 4) count operation ? count direction (increment or decrement) is set by a two-phase pulse signal. ? reload/free-run type can be selected. reload function: the contents of the reload register are reloaded into the counter and the count continues when the timer underflows or overflows. free-running function: the counter continues running without reloading when the timer underflows or overflows. number of counting (ffffh - n + 1): when incrementing n + 1: for decrementing n: setting value of the tai register, 0000h to ffffh count start condition the tais bit in the tabsr register is set to 1 (count starts) count stop condition the tais bit is set to 0 (count stops) interrupt request generation timing when the timer overflows or underflows taiin pin function two-phase pulse input taiout pin function two-phase pulse input read from timer a read from the tai register returns a counter value write to timer ? a write to the tai register while the count is stopped: the value is written to both the reload register and the counter. ? a write to the tai register while counting: the value is written to the reload register (it is transferred to the counter at the next reload timing). (1) selectable function (2) ? normal processing operation (timers a2 and a3) while a high-level (?h?) signal is applied to the tajout pin (j = 2, 3), the timer increments a counter value at the rising edge of the tajin pin or decrements a counter value at the falling edge. ? multiply-by-4 processing operation (timers a3 and a4) the timer increments the counter value in the following timings: -at the rising edge of takin while takout is ?h? (k = 3, 4) -at the falling edge of takin while takout is ?l? -at the rising edge of takout while takin is ?l? -at the falling edge of takout wh ile takin is ?h? the timer decrements the counter in the following timings: -at the rising edge of takin while takout is ?l? -at the falling edge of takin while takout is ?h? -at the rising edge of takout while takin is ?h? -at the falling edge of takout wh ile takin is ?l? ? counter reset by a z-phase pulse signal input (timer a3) the counter value is cleared to 0 by a z-phase pulse signal input m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 159 of 352 rej09b0385-0100 figure 15.16 operation in event counter mode when handling two-phase pulse signals on timers a2, a3, and a4 normal processing operation (timer a2 and timer a3) set to 0 by an interrupt request acknowledgement or by program. m m+1 m+2 m+1 m m-1 1 0 ffff fffe ffff 0 tajout tajin m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 160 of 352 rej09b0385-0100 15.1.2.1 counter reset by tw o-phase pulse signal processing the counter value of timer can be set to 0 by a z-ph ase pulse signal input (counter reset) when processing two-phase pulse signals. this function can be used when al l the following conditions are met; timer a3 event counter mode, two-phase pulse signal processing, free-running count operation type, and multiply-by-4 processing. the z-phase pulse signal is applied to the int2 pin. when the tazie bit in the onsf register is set to 1 (z -phase input enabled), z-phase pulse input is enabled to reset the counter. to reset the counter by a z-phase pulse input, set the ta3 register to 0000h beforehand. a z-phase pulse input is enabled when th e edge of a signal applied to the int2 pin is detected. the pol bit in the int2ic register can determine the edge polarity. th e z-phase pulse must have a pulse width of one timer a3 count source cycle or more. figure 15.17 shows rela tions between two-phase pulses (a-phase and b-phase) and the z-phase pulse. z-phase pulse input resets the counter in the next count source timing followed a z-phase pulse input. a timer a3 interrupt request is generated twice in a ro w if a timer a3 overflow or underflow, and the counter reset by an int2 input occur at the same time. do not generate a timer a3 interrupt request when this function is used. figure 15.17 relations between two-phase pulses (a-phase and b-phase) and z-phase pulse pulse width of one count source cycle or more is required note: 1. example when the risi ng edge of int2 is selected. ta3out (a phase) m m + 1 1 23 45 ta3in (b phase) count source int2 (1) (z phase) counter value 6 m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 161 of 352 rej09b0385-0100 15.1.3 one-shot timer mode when a trigger occurs, the counter decrements until unde rflows. then, the counter is reloaded and stops until the next trigger occurs. table 15.6 lists specifications of one-shot timer mode. figure 15.18 shows a one-shot timer mode operation. table 15.6 specifications of one-shot timer mode notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. wait for one count source cycle or mo re to write after the count starts. item specification count source f1, f8, f2n (1) , fc32 count operation ? counter decrements when the counter reaches 0000h, the counter is reloaded and stops until the next trigger occurs. if a trigger occurs while counting, the contents of the reload register are reloaded into the counter and the count continues. number of counting n times n: setting value of the tai register (i = 0 to 4), 0000h to ffffh (but the counter does not run if n = 0000h) count start condition a trigger, selectable from the following, occurs while the tais bit in the tabsr register is set to 1 (count starts): ? the taios bit in the onsf register is set to 1 (timer starts) ? an external trigger is applied to taiin pin ? timer b2 overflows or underflows, ? timer aj overflows or underflows (j = i - 1, except j = 4 if i = 0), ? timer ak overflows or underflows (k = i + 1, except k = 0 if i = 4) count stop condition ? after the counter reaches 0000h and the counter value is reloaded ? when the tais bit is set to 0 (count stops) interrupt request generation timi ng when the counter reaches 0000h taiin pin function trigger input taiout pin function pulse output read from timer a read from the tai register returns undefined value write to timer ? a write to the tai register while the count is stopped: the value is written to both the reload register and the counter. ? a write to the tai register while counting: the value is written to the reload register (it is transferred to the counter at the next reload timing). (2) selectable function pulse output function ?l? is output while the count stops. ?h? is output while counting. m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 162 of 352 rej09b0385-0100 figure 15.18 operation in one-shot timer mode (timer a) ffffh m 0000h count starts re-trigger input count starts count starts 1 / fj x m 1 / fj x (m + 1) fj: frequency of the count source (f1, f8, f2n (1) , fc32) i = 0 to 4 tais bit in the tabsr register contents of the counter m = contents of the reload register ir bit in the taiic register 0 1 0 1 one-shot pulse output from the taiout pin l h write signal to taios bit in the onsf register note: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). (conditions) taimr register: bits tmod1 and tmod0 are set to 10b (one-shot timer mode). the mr2 bit is set to 0 (the taios bit in the onsf register is enabled). reload reload reload count stops count stops count stops set to 0 by an interrupt request acknowledgement or by program m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 163 of 352 rej09b0385-0100 15.1.4 pulse width modulation mode in pulse width modulation mode, the timer outputs pu lse signals of a given widt h repeatedly. the counter functions as an 8-bit pulse width modulator or 16-bit pulse width modulator. table 15.7 lists specifications of pulse width modulati on mode. figures 15.19 and 15.20 show examples of a 16-bit pulse width modulator and 8-bit pulse width modulator operations. table 15.7 specifications of pulse width modulation mode note: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. wait for one count source cycle or mo re to write after the count starts. item specification count source f1, f8, f2n (1) , fc32 count operation ? counter decrements (the counter functions as the 8-bit or 16-bit pulse width modulator.) the contents of the reload register are reloaded at the rising edge of the pwm pulse and the counter decrements. the count continues even if the re-trigger occurs while counting. 16-bit pwm ? ?h? width = n / fj n: setting value of the tai register (i = 0 to 4), 0000h to fffeh fj: count source frequency ?cycle = (2 16 - 1) / fj the cycle is fixed to this value 8-bit pwm ? ?h? width = n x (m + 1) / fj ?cycle = (2 8 - 1) x (m + 1) / fj m: setting value of low-order bit address of the tai register, 00h to ffh n: setting value of high-order bit address of the tai register, 00h to feh count start condition when a trigger is not us ed (the mr2 bit in the taimr register is 0): set the tais bit in the tabsr register to 1 when a trigger is used (the mr2 bi t in the taimr register is 1): a trigger, selectable from the followin g occurs while the tais bit in the tabsr register is set to 1(count starts): ? an external trigger is applied to taiin pin ? timer b2 overflows or underflows ? timer aj overflows or underflows (j = i - 1, except j = 4 if i = 0) ? timer ak overflows or underflows (k = i + 1, except k = 0 if i = 4) count stop condition the tais bit is set to 0 (count stops) interrupt request generation timing at the falling edge of the pwm pulse taiin pin function trigger input taiout pin function pulse output read from timer a read from the tai register returns undefined value write to timer ? a write to the tai register while the count is stopped: the value is written to both the reload register and the counter. ? a write to the tai register while counting: the value is written to the reload register (it is transferred to the counter at the next reload timing). (2) m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 164 of 352 rej09b0385-0100 figure 15.19 16-bit pulse width modulator operation (timer a) count source input to the taiin pin set to 0 by an interrupt request acknowledgement or by program ir bit in the taiic register 1 / fj (2 16 - 1) pwm pulse output from the taiout pin "h" "h" "l" "l" 1 0 no trigger is generated by this signal 1 / fj m i = 0 to 4 fj: count source frequency (f1, f8, f2n (1) , fc32) m: setting value of the tai register (0000h to fffeh) (conditions) tai register is set to 0005h. taimr register: mr1 bit is set to 1 (rising edge of signal appl ied to the taiin pin) note: 1. bits cnt3 to cnt0 in the tcspr register select no divis ion (n = 0) or divide-by-2n (n = 1 to 15). when the tais bit is set to 0 (count stops) while the taiout output is "h", the taiout output becomes "l" and the ir bit is set to 1 (interrupt requested). 1 0 tais bit in the tabsr register set to 1 by program set to 0 by program count starts end of 1 cycle count stops m32c/8a group 15. timers (timer a) rev.1.00 jul 15, 2007 page 165 of 352 rej09b0385-0100 figure 15.20 8-bit pulse width modulator operation (timer a) tais bit in the tabsr register ir bit in the taiic register pwm pulse output from taiout pin i = 0 to 4 fj: count source frequency (f1, f8, f2n (1) , fc32) n: high-order bits in the tai register (00h to feh) m: low-order bits in the tai register (00h to ffh) (conditions) high-order bits in the tai register are set to 02h. low-order bits in the tai register are set to 02h. taimr register: the mr1 bit is set to 0 (falling edge of signal applied to the taiin pin.) signal applied to taiin pin when the tais bit is set to 0 (co unt stops) while the taiout output is "h", the taiout output becomes "l" and the ir bit becomes 1 (interrupt requested). underflow signal of 8-bit prescaler count starts end of 1 cycle count stops count source h l 1 0 h l 1 0 1 / fj x (m+1) x (2 8 -1) set to 1 by program set to 0 by program 1 / fj x (m+1) x n set to 0 by an interrupt request acknowledgement or by program notes: 1. bits cnt3 to cnt0 in the tcspr register select no division ( n = 0) or divide-by-2n (n = 1 to 15). 2. the 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler. m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 166 of 352 rej09b0385-0100 15.2 timer b timer b contains the following three modes. bits tmod1 and tmod0 in the tbimr register (i = 0 to 5) determine which mode is used. ? timer mode: the timer counts the internal count source. ? event counter mode: the timer counts overflows/underflows of another timer, or the external pulses. ? pulse period measurement mode, pulse width measur ement mode: the timer measures the pulse period or pulse width of the external signal. figure 15.21 shows a block diagram of timer b. figures 15.22 to 15.26 show the registers associated with timer b. table 15.8 shows tbiin pin settings (i = 0 to 5). figure 15.21 timer b block diagram reload register 00 01 10 11 clock source select tbis high-order bits of data bus low-order bits of data bus 8 low-order bits 8 high-order bits tbiin 01: event counter mode 00: timer mode 10: pulse period and pulse width measurement mode tmod1 and tmod0 tck1 and tck0 i= 0 to 5 j = i - 1, except j = 2 if i = 0, j = 5 if i = 3. notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. overflow signal or underflow signal. tck1 and tck0, tmod1 and tmod0: bits in the tbimr register tbis: bit in the tabsr register or the tbsr register tbi addresses tbj timer b0 0351h 0350h timer b2 timer b1 0353h 0352h timer b0 timer b2 0355h 0354h timer b1 timer b3 0311h 0310h timer b5 timer b4 0313h 0312h timer b3 timer b5 0315h 0314h timer b4 f1 f8 f2n (1) fc32 counter tbj overflow (2) polarity switching and edge pulse counter reset circuit 0 1 tck1 m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 167 of 352 rej09b0385-0100 figure 15.22 tb0mr to tb5mr registers in timer mode b7 0 0 0 b6 b5 b4 b1 b2 b3 symbol tb0mr to tb5mr address 035bh, 035ch, 035dh, 031bh, 031ch, 031dh after reset 00xx 0000b b0 function bit symbol bit name rw mr3 tck1 rw rw rw ? mr1 count source select bits tck0 timer bi mode register (i = 0 to 5)(timer mode) tmod1 rw rw mr0 b1 b0 0 0: timer mode operating mode select bits tmod0 rw disabled in timer mode. can be set to either 0 or 1 disabled in timer mode. write 0. read as undefined value. b7 b6 0 0: f1 0 1: f8 1 0: f2n (1) 1 1: fc32 note: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). to select f2n, set the cst bit in the tcspr regi ster to 1 before setting bits tck1 and tck0 to 10b. mr2 rw ? registers tb0mr and tb3mr: set to 0 in timer mode. registers tb1mr, tb2mr, tb4mr, and tb5mr: unimplemented. write 0. read as undefined value. m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 168 of 352 rej09b0385-0100 figure 15.23 tb0mr to tb5mr registers in event counter mode b3 b2 0 0: falling edges of an external signal counted 0 1: rising edges of an external signal counted 1 0: falling and rising edges of an external signal counted 1 1: do not set to this value b7 1 0 0 b6 b5 b4 b1 b2 b3 symbol tb0mr to tb5mr address 035bh, 035ch, 035dh, 031bh, 031ch, 031dh after reset 00xx 0000b b0 function bit symbol bit name rw mr3 tck1 rw rw rw ? mr1 tck0 timer bi mode regist er (i = 0 to 5)(event counter mode) tmod1 rw rw mr0 b1 b0 0 1: event counter mode operating mode select bits tmod0 rw disabled in event counter mode. write 0. read as undefined value. notes: 1. bits mr1 and mr0 are enabled when the tck1 bit is set to 0. bits mr1 and mr0 can be set to either 0 or 1 when the tck1 bit is set to 1. 2. j = i - 1, except j = 2 if i = 0 and j = 5 if i = 3. mr2 rw ? registers tb0mr and tb3mr: set to 0 in event counter mode. registers tb1mr, tb2mr, tb4mr, and tb5mr: unimplemented. write 0. read as undefined value. count polarity select bits (1) disabled in event counter mode. can be set to either 0 or 1 0: signal applied to the tbiin pin 1: tbj overflows or underflows (2) event clock select bit m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 169 of 352 rej09b0385-0100 figure 15.24 tb0mr to tb5mr registers in pulse period measurement mode, pulse width measurement mode b7 0 1 b6 b5 b4 b1 b2 b3 symbol tb0mr to tb5mr address 035bh, 035ch, 035dh, 031bh, 031ch, 031dh after reset 00xx 0000b b0 function bit symbol bit name rw mr3 tck1 rw rw rw ro mr1 tck0 timer bi mode regist er (i = 0 to 5) (pulse period measurement mode, pulse width measurement mode) tmod1 rw rw mr0 b1 b0 1 0: pulse period measurement mode pulse width measurement mode operating mode select bits tmod0 rw notes: 1. bits mr1 and mr0 deter mine the following measurement modes: pulse period measurement 1 (bits mr1 and mr0 are set to 00b): measures the width between the falling edges of a pulse pulse period measurement 2 (bits mr1 and mr0 bits are set to 01b): measures the width between the rising edges of a pulse pulse width measurement (bits mr1 and mr0 bits are set to 10b): measures the width between a fa lling edge and a rising edge of a pulse, and between a rising edge and a falling edge of a pulse 2. the mr3 bit is undefined when reset. 3. to set the mr3 bit to 0 (no over flow), wait for one or more cou nt source cycles to wri te a 0 to the tbimr register after the m r3 bit becomes 1 (overflow), wh ile the tbis bit in tabsr or t bsr register is set to 1 (count starts). 4. bits cnt3 to cnt0 in the tcspr register select no divi sion (n = 0) or divide-by-2n (n = 1 to 15). to select f2n, set th e cst bit in the tcspr register to 1 before setting bits tck1 and tck0 to 10b. mr2 rw ? registers tb0mr and tb3mr: set to 0 in pulse period measur ement mode, pulse wi dth measurement mode. registers tb1mr, tb2mr, tb4mr, and tb5mr: unimplemented. write 0. read as undefined value. measurement mode select bits (1) b3 b2 0 0: pulse period measurement 1 0 1: pulse period measurement 2 1 0: pulse width measurement 1 1: do not set to this value b7 b6 0 0: f1 0 1: f8 1 0: f2n (4) 1 1: fc32 count source select bits timer bi overflow flag (2) 0: no overflow has occurred 1: overflow has occurred (3) m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 170 of 352 rej09b0385-0100 figure 15.25 tb0 to tb5 registers b15 b8 b7 symbol tb0 to tb2 tb3 to tb5 address 0351h - 0350h, 0353h - 0352h, 0355h - 0354h 0311h - 0310h, 0313h - 0312h, 0315h - 0314h after reset undefined undefined b0 setting range mode function rw timer bi register (1) (i = 0 to 5) rw 0000h to ffffh if a count source frequency is fj, and the setting value of the tbi register is n, the counter cycle is (n+1). timer mode rw 0000h to ffffh if the setting value of the tbi register is n, the count times are (n+1) (2) event counter mode pulse period measurement mode, pulse width measurement mode increment the counter between one valid edge and another valid edge of a pulse applied to the tbiin pin ? ro notes: 1. read and write this register in 16-bit units. 2. timer bi counts overflows/underflow s of another timer, or the external pulses. m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 171 of 352 rej09b0385-0100 figure 15.26 tabsr register, tbsr register 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts function b7 b6 b5 b4 b1 b2 b3 symbol tabsr address 0340h after reset 00h b0 bit symbol bit name rw tb0s tb2s timer a3 count start bit timer b2 count start bit rw rw rw rw ta4s rw ta3s timer b0 count start bit timer b1 count start bit tb1s count start register timer a4 count start bit timer a1 count start bit ta1s rw timer a2 count start bit rw ta2s 0: count stops 1: count starts timer a0 count start bit ta0s rw b7 b6 b5 b4 b1 b2 b3 symbol tbsr address 0300h after reset 000x xxxxb b0 function bit symbol bit name rw timer b3, b4, b5 count start register timer b3 count start bit tb3s rw unimplemented. write 0. read as undefined value. ? (b4-b0) ? 0: count stops 1: count starts tb4s rw rw tb5s 0: count stops 1: count starts timer b4 count start bit 0: count stops 1: count starts timer b5 count start bit m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 172 of 352 rej09b0385-0100 table 15.8 tbiin pin settings (i=0 to 5) note: 1. set the pd9 or ps3 register immediately after the prc2 bi t in the prcr register is set to 1 (write enable). do not generate an interrupt or a dma or dmacii transfer between these two instructions. pin function bit setting pd7, pd9 (1) registers ps1, ps3 (1) registers p7_1 tb5in pd7_1 = 0 ps1_1 = 0 p9_0 tb0in pd9_0 = 0 ps3_0 = 0 p9_1 tb1in pd9_1 = 0 ps3_1 = 0 p9_2 tb2in pd9_2 = 0 ps3_2 = 0 p9_3 tb3in pd9_3 = 0 ps3_3 = 0 p9_4 tb4in pd9_4 = 0 ps3_4 = 0 m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 173 of 352 rej09b0385-0100 15.2.1 timer mode in timer mode, the timer counts an internally generated count source. table 15.9 lists specifications of timer mode. figu re 15.27 shows a timer mode operation (timer b). table 15.9 specifications of timer mode notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. wait for one count source cycle or mo re to write after the count starts. figure 15.27 operation in timer mode (timer b) item specification count source f1, f8, f2n (1) , fc32 count operation ? counter decrements when the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. counter cycle n + 1 fj: count source frequency fj n: setting value of the tbi register (i=0 to 5), 0000h to ffffh count start condition the tbis bit in the tabsr or tbsr register is set to 1 (count starts) count stop condition the tbis bit is set to 0 (count stops) interrupt request generation timing when the timer underflows tbiin pin function programmable i/o port read from timer a read from the tbi register returns a counter value. write to timer ? a write to the tbi register while the count is stopped: the value is written to both the reload register and the counter. ? a write to the tbi register while counting: the value is written to the reload register (it is transferred to the counter at the next reload timing). (2) count starts ffffh n count stops i = 0 to 5 (condition) tbimr register: bits tmod1 and tmod0 are set to 00b (timer mode). tbis bit in the tabsr or tbsr register contents of the counter n = contents of the reload register 0000h ir bit in the tbiic register 0 1 underflow reload underflow reload 0 1 set to 0 by an interrupt request acknowledged or by program count resumes m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 174 of 352 rej09b0385-0100 15.2.2 event counter mode in event counter mode, the timer counts overflows/underflows of another timer, or the external pulses. table 15.10 lists specifications of event counter mode. figure 15.28 shows an event counter mode operation. table 15.10 specifications of event counter mode note: 1. wait for one count source cycle or mo re to write after the count starts. figure 15.28 operation in event counter mode (timer b) item specification count source ? external signal applied to the tbiin pin (i = 0 to 5) (valid edge can be selected by program) ? tbj overflows or underflows (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3) count operation ? counter decrements when the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. number of counting (n + 1) times n: setting value of the tbi register 0000h to ffffh count start condition the tbis bit in the tabsr or tbsr register is set to 1 (count starts) count stop condition the tbis bit is set to 0 (count stops) interrupt request generation timing when the timer underflows tbiin pin function count source input read from timer a read from the tbi register returns a counter value. write to timer ? a write to the tbi register while the count is stopped: the value is written to both the reload register and the counter. ? a write to the tbi register while counting: the value is written to the reload register (it is transferred to the counter at the next reload timing). (1) count starts ffffh n tbis bit in the tabsr or tbsr regsiter contents of the counter n = contents of the reload register 0000h ir bit in the tbiic regsiter 0 1 (condition) tbimr register: bits tmod1 and tmod0 are set to 01b (event counter mode) bits mr1 and mr0 are set to 00b (count the falling edge of the external signal) the tck1 bit is set to 0 (signal input to tbiin pin) underflow reload count stops 0 1 set to 0 by an interrupt request a cknowledgement or by program count resumes input to the tbiin pin l h i = 0 to 5 m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 175 of 352 rej09b0385-0100 15.2.3 pulse period measurement mode , pulse width measurement mode in pulse period measurement mode and pulse width m easurement mode, the timer measures pulse period or pulse width of the external signal. table 15.11 shows specifications in pulse period measurement mode and puls e width measurement mode. figure 15.29 shows a pulse period measurement operation. figure 15.3 0 shows a pulse width measurement operation. table 15.11 specifications of pulse period measurement mode, pulse width measurement mode notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. an interrupt request is not generated when the first valid edge is input after the count starts. 3. to set the mr3 bit to 0 (no overflow), wait for one or more count source cycles to write to the tbimr register after the mr3 bit becomes 1, while the tbis bit is set to 1. 4. a value read from the tbi register is undefined until the second valid edge is detected after the count starts. item specification count source f1, f8, f2n (1) , fc32 count operation ? counter increments the counter value is transferred to the reload register when the valid edge of a pulse is detected. then the counter becomes 0000h and the count continues. count start condition the tbis bit (i = 0 to 5) in the tabsr or tbsr register is set to 1 (count starts) count stop condition the tbis bit is set to 0 (count stops) interrupt request generation timing ? when the valid edge of a pulse is input (2) ? when the timer overflows (3) the mr3 bit in the tbimr register is set to 1 (overflow) simultaneously. tbiin pin function pulse input read from timer a read from the tbi register returns the contents of the reload register (measurement results) (4) write to timer the tbi register cannot be written m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 176 of 352 rej09b0385-0100 figure 15.29 operation in pulse period measurement mode (timer b) ffffh n tbis bit in the tabsr register or tbsr register contents of the counter (n = contents of the reload register) 0000h ir bit in the tbiic register 0 1 pulse input to tbiin pin (2) i = 0 to 5 notes: 1. counter is reset due to the completion of the measureme nt. 2. if an overflow and a valid edge input occur simultaneou sly, an interrupt request is generated only once, which results in the valid edge not being recognized. do not let an overflow occur. 0 1 l h set to 0 by an interrupt request a cknowledgement or by program 1st valid edge 2nd valid edge (note 1) transfer timing from counter to reload register tbi register transfer (undefined value) transfer (measured value n) undefined value n m32c/8a group 15. timers (timer b) rev.1.00 jul 15, 2007 page 177 of 352 rej09b0385-0100 figure 15.30 operation in pulse width measurement mode (timer b) i = 0 to 5 notes: 1. counter is reset due to the completion of the measureme nt. 2. overflow 3. to set the mr3 bit to 0 (no overflow), wait for one or more count source cycles to write a 0 to the tbimr register after the mr3 bit becomes 1 (overflow), while the tbis bit in tabsr or tbsr register is set to 1 (count starts). 4. determine whether an interrupt source is a valid edge input or an overflow by reading the port level in the tbi interrupt routine. pulse input to tbiin pin tbis bit in the tabsr or tbsr register h l 1 0 ir bit in the tbiic register transfer (undefined value) transfer (measured value n) mr3 bit in the tbimr register 1 0 1 0 2nd valid edge ffffh n contents of the counter n = contents of the reload register 0000h transfer timing from counter to reload register set to 0 by an interrupt acknowledgement or by program tbi register n undefined value 10000h + n 1st valid edge (note1) (note2) (note1) (note 3) (note 4) (note 4) m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 178 of 352 rej09b0385-0100 16. three-phase motor control timer function the pwm waveform can be output by using timers b2, a1, a2, an d a4. timer b2 is used for the carrier wave control, and timers a4, a1, and a2 for th e u-, v-, and w-phase pwm control. table 16.1 lists specifications of the three-phase motor control timer functions. table 16.2 lists pin settings. figure 16.1 shows a block diagram. figures 16.2 to 16.10 show regi sters associated with the th ree-phase motor control timer function. table 16.1 specifications of three-phase motor control timers item specification control method three-phase full wave method modulation modes ? triangular wave modulation mode ? sawtooth wave modulation mode active level selectable either active high or active low timers to be used ? timer b2 (carrier wave cycle control: used in timer mode) ? timers a4, a1, and a2 (u-, v-, w-phase pwm control: used in one-shot timer mode): short circuit prevention features ? prevention function against upper and lower arm short circuit caused by program errors ? arm short circuit prevention function using dead time timer ? forced cutoff function by nmi input m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 179 of 352 rej09b0385-0100 figure 16.1 three-phase motor control timer function block diagram fdt dtt register value written to inv03 bit write signal to inv03 bit inv04 inv02 u-phase w-phase inv06 write signal to idbi register s q r "1" write signal to inv07 bit transfer trigger (1) d t q d t q dead timer timer start trigger inv16 data bus data bus d q t d q t d q dvb1 dvb0 d q data bus data bus d q t d q t d q dv1 dv0 d q inv15 fdt dead timer timer start trigger dead timer timer start trigger v-phase upper/ lower arm short circuit detection signal v-phase output control circuit reload register 0 1 transfer trigger transfer trigger dtt register dtt register counter ictb2 register interrupt request timer b2 interrupt request inv02 1 0 timer b2 reload register tb2 register inv10 write signal to tb2 register f1 ta1 register ta11 register timer a1 reload register f1 d q t q inv11 timer a1 reload control signal start trigger pwcon 0 1 timer a1 reload control signal timer a1 reload control signal inv01 inv11 inv00 inv03 d q t r inv05 reset nmi inv14 0 1 inv14 v v 0 1 d q t d q t three-phase output shift register three-phase output shift register u u u-phase output c ontrol circuit w w w-phase output control circuit note: 1. when the inv06 bit is se t to 0 (triangular wave modulat ion mode), a transfer trigger i s generated at the first timer b 2 underflow after writing to the idbi register (i = 0, 1 ). inv00 to inv07: bits in the invc0 register inv10 to inv15: bits in the invc1 register dvi, dvbi: bits in the idbi register (i = 0, 1) pwcon: bit in the tb2sc register inv06 start trigger start trigger m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 180 of 352 rej09b0385-0100 figure 16.2 invc0 register b7 b6 b5 b4 b1 b2 b3 three-phase pwm control register 0 (1) symbol invc0 address 0308h bit symbol bit name rw inv00 after reset 00h rw b0 function ictb2 count condition select bits inv01 rw rw b1 b0 0 0: 0 1: 1 0: timer b2 underflow at the rising edge of the timer a1 reload control signal (2) (every odd-numbered timer b2 underflow) 1 1: timer b2 underflow at the falling edge of the timer a1 reload control signal (2) (every even-numbered timer b2 underflow) inv02 three-phase motor control timer function enable bit (3) 0: three-phase motor control timer function not used 1: three-phase motor control timer function used (4,5) inv03 three-phase motor control timer output control bit 0: three-phase motor control timer output disabled (5,6) 1: three-phase motor control timer output enabled modulation mode select bit (9) 0: triangular wave modulation mode 1: sawtooth wave modulation mode (10) inv06 rw rw rw inv04 upper and lower arm simultaneous turn-on disable bit 0: simultaneous turn-on enabled 1: simultaneous turn-on disabled inv05 upper and lower arm simultaneous turn-on detect flag 0: not detected 1: detected (7) ro software trigger select bit transfer trigger is generated when the inv07 bit is set to 1. trigger for the dead time timer is also generated when the inv06 bit is set to 1. this bit is read as 0. inv07 rw notes: 1. set the invc0 register after the prc1 bit in the p rcr register is set to 1 (write enable). set bits inv06 and inv02 to inv00 while timers a1,a2, a4, and b2 are stopped. 2. set the inv01 bit to 1 after setting a value to the ic tb2 register. also, when the inv 01 bit is set to 1, set the time r a1 count start bit to 1 prior to the first timer b2 underflow. 3. set pins after the inv02 bit is set to 1. refer to the table, pin settings when using three-phase motor control timer function . 4. set the inv02 bit to 1 to operate the dead time ti mer, u-, v-, and w-phase output cont rol circuits, and ictb2 counter. 5. when the inv03 bit is set to 0 and the inv02 bit to 1, pins u, u, v, v, w, and w (including when other output functions are assiged to these pins) are all placed in high-impedance states. 6. the inv03 bit becomes 0 when one of the following occurs: -reset -the both upper and lower arms output the active level signals at the same time while the inv04 bit is set to 1 -the inv03 bit is set to 0 by program -signal applied to the nmi pin changes from "h" to "l" (while an "l" is applied to the nmi pin, the inv03 bit canno t be set to 1). 7. the inv05 bit cannot be set to 1 by program. to set the inv05 bit to 0, write a 0 to the inv04 bit. timer b2 underflow m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 181 of 352 rej09b0385-0100 figure 16.3 invc1 register b7 b6 b5 b4 b1 b2 b3 three-phase pwm control register 1 (1) symbol invc1 address 0309h bit symbol bit name rw after reset 00h b0 function inv10 rw rw 0: timer b2 underflow 1: timer b2 underflow and a write to the tb2 register timers a1, a2, and a4 start trigger select bit inv11 timers a11, a21, and a41 control bit 0: timers a11, a21, and a41 not used (three-phase mode 0) 1: timers a11, a21, and a41 used (three-phase mode 1) inv12 dead time timer count source (fdt) select bit 0: f1 1: f1 divided by 2 dead time timer trigger select bit 0: falling edge of one-shot pulse of timer (a4, a1, and a2 (3) ) 1: rising edge of the three-phase output shift register (u-, v-, w-phase) inv16 rw 0 ro inv13 carrier wave rise/fall detect flag (2) 0: timer b2 underflow occurred an even number of times 1: timer b2 underflow occurred an odd number of times inv14 active level control bit 0: active low 1: active high rw notes: 1. set the invc1 register after the prc1 bit in the p rcr register is set to 1 (write enable). set the invc1 register while timers a1, a2, a4, and b2 are stopped. 2. the inv13 bit is enabled only when the inv06 bit is set to 0 (triangular wave modulation mode) and the inv11 bit to 1. 3. if the following conditions are all met, set the inv16 bit to 1. - the inv15 bit is set to 0 - bits dij (i = u, v or w, j = 0, 1) and dibj in the idbj register always have different values when the inv03 bit in the in vc0 register is se t to 1 (three-phase control timer output enabled). (the upper arm and lower arm alwa ys output opposite level signals at any time except dead time.) if any of the above conditions is not met, set the inv16 bit to 0. rw ? (b7) reserved bit set to 0 rw inv15 dead time disable bit 0: dead time enabled 1: dead time disabled rw m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 182 of 352 rej09b0385-0100 figure 16.4 tb2mr register when using three-phase motor control timer function b7 0 0 0 b6 b5 b4 b1 b2 b3 symbol tb2mr address 035dh after reset 00xx 0000b b0 function bit symbol bit name rw mr3 tck1 rw rw rw rw mr2 ? mr1 count source select bits tck0 timer b2 mode register tmod1 rw rw mr0 set to 00b (timer mode) to use the three-phase motor control timer function operating mode select bits tmod0 rw disabled to use the three-phase motor control timer function. can be set to either 0 or 1. set to 00b (f1) to use the three-phase motor control timer function set to 0 to use the three-phase motor control timer function unimplemented. write 0. read as undefined value. m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 183 of 352 rej09b0385-0100 figure 16.5 ta1mr, ta2mr, and tm4mr registers when using three-phase motor control timer function b7 0 1 0 0 1 0 b6 b5 b4 b1 b2 b3 symbol ta1mr, ta2mr, ta4mr address 0357h, 0358h, 035ah after reset 00h b0 function bit symbol bit name rw mr3 tck1 rw rw rw rw mr2 rw mr1 count source select bits tck0 timer ai mode regist er (i = 1, 2, 4) tmod1 rw rw ? (b2) set to 01b (one-shot timer mode) to use the three-phase motor control timer function operating mode select bits tmod0 rw reserved bit set to 0 to use the three-phase motor control timer function set to 00b (f1) to use the three-phase motor control timer function external trigger select bit set to 1 (selected by the trgsr register) to use the three-phase motor control timer function trigger select bit set to 0 to use the three-phase motor control timer function set to 0 m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 184 of 352 rej09b0385-0100 figure 16.6 trgsr register when using three-phase motor control timer function trigger select register symbol trgsr address 0343h bit symbol rw ta1tgl after reset 00h note: 1. overflow or underflow. ta1tgh rw rw b7 b6 b5 b4 b1 b2 b3 b0 bit name timer a1 trigger select bits function set to 01b (tb2 underflow) to use the v-phase output control circuit ta2tgl ta2tgh rw rw timer a2 trigger select bits set to 01b (tb2 underflow) to use the w-phase output control circuit ta3tgl ta3tgh rw rw timer a3 trigger select bits b5 b4 0 0: input to the ta3in pin selected 0 1: tb2 overflow selected (1) 1 0: ta2 overflow selected (1) 1 1: ta4 overflow selected (1) ta4tgl ta4tgh rw rw timer a4 trigger select bits set to 01b (tb2 underflow) to use the u-phase output control circuit m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 185 of 352 rej09b0385-0100 figure 16.7 tb2sc register, ictb2 register bit name b7 0 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol tb2sc address 035eh after reset 00h b0 function bit symbol rw timer b2 special mode register (1) rw rw pwcon timer b2 reload timing switch bit 0: timer b2 underflow 1: timer b2 underflow at the rising edge of the timer a1 reload control signal (every odd-numbered timer b2 underflow) note: 1. set the tb2sc register after the prc1 bit in the prcr register is set to 1 (write enable). ? (b7-b1) reserved bits set to 0 timer b2 interrupt generation frequency set counter (1, 2) symbol ictb2 address 030dh rw after reset undefined notes: 1. read-modify-write instructions cannot be used to set the ictb2 register. refer to usage notes for details. 2. if the inv01 bit in the invc0 register is set to 1, set the ictb2 register while the tb 2s bit is set to 0 (count stops) . if the inv01 bit is set to 0, do not set the ictb2 register when timer b2 underflows, regardless of the tb2s bit setting. wo ? b7 b0 function unimplemented. write 0. read as undefined value. 1 to 15 setting range -when the inv01 bit in the invc0 register is set to 0 (the ictb2 counter increments at every timer b2 underflows) and a setting value is n, the timer b2 inte rrupt request is generated every n-th timer b2 underflow. -when bits inv01 and inv00 are set to 10b (the ictb2 counter increments when the timer b2 underflow at the rising edge of the timer a1 reload control signal) and a setting value is n, the first timer b2 interrupt request is generated at the (2n-1)th timer b2 underflow. from the 2nd time on, the request is generated every 2n-th timer b2 underflow. -when bits inv01 and inv00 are set to 11b (the ictb2 counter increments when the timer b2 underflow occurs at the falling edge of the timer a1 reload control signal) and a setting value is n, the timer b2 interrupt request is generated every 2n-th timer b2 underflow. b6 b5 b4 b3 m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 186 of 352 rej09b0385-0100 figure 16.8 tb2 register, dtt register when us ing three-phase motor control timer function symbol tb2 address 0355h - 0354h after reset undefined function rw timer b2 register (1) rw if a setting value is n, f1 is divided by n+1. timers a1, a2, and a4 start ev ery time timer b2 underflows. note: 1. read and write this register in 16-bit units. setting range 0000h to ffffh b15 b0 b7 b8 symbol dtt address 030ch after reset undefined function rw dead time timer (1, 2, 3) wo this one-shot timer is used to delay the timing for a turn-on signal to be switched to its active level in order to prevent the upper and lower arm short circuit. if a setting value is n, the count source is counted n times after the start trigger occurs, and then the timer stops. notes: 1. read-modify-write instructions c annot be used to set the dtt register. refer to usage notes for details. 2. the dtt register setting is enabled when the inv15 bi t in the invc1 register is se t to 0 (dead time enabled). no dead time is generated when the inv15 bit is set to 1 (dead time disabled). 3. the inv16 bit in the invc1 register determines the st art trigger of the dtt register. the inv12 bit determines the cou nt source. setting range 01h to ffh b7 b0 m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 187 of 352 rej09b0385-0100 figure 16.9 ta1, ta2, ta4, ta11, ta21, an d ta41 registers, idb0, idb1 registers symbol ta1, ta2, ta4 ta11, ta21, ta41 address 0349h - 0348h, 034bh - 034ah, 034fh - 034eh 0303h - 0302h, 0305h - 0304h, 0307h - 0306h after reset undefined undefined function rw timer ai, ai1 register (1, 2, 3, 4, 5) (i = 1, 2, 4) wo if a setting value is n, f1 is counted n times after a start trigger occurs, and then the timer stops. output signal level for each phase changes when timers a1, a2, or a4 stop. notes: 1. write these registers in 16-bit units. read-modify-wri te instructions cannot be used to set registers tai and tai1. r efer to usage notes for details. 2. if the tai or tai1 register is set to 0000h, the counter does not start and the time r ai interrupt is not generated. 3. when the inv15 bit in the invc1 register is set to 0 (dead timer enabled), an output signal is switched to its active l evel with delay simultaneously with the dead time timer underflow. 4. when the inv11 bit is set to 0 (timers a11, a21, and a41 are not used (three-phase mode 0)), the contents of the tai re gister are transferred to the reload register by a timer ai start trigger . when the inv11 bit is set to 1 (timers a11, a21, and a41 a re used (three-phase mode 1)), the contents of the tai1 register are transferred by the first timer ai start trigger, and then con tents of the tai register are transferred by the next timer ai star t trigger. subsequently, the content s of registers tai1 and tai ar e transferred alternately to the reload register by each timer ai start trigger. 5. do not set registers tai and tai1 in the timer b2 underflow timing. setting range 0000h to ffffh b15 b0 b7 b8 three-phase output buffer register i (1) (i = 0, 1) symbol idb0, idb1 address 030ah, 030bh bit symbol rw dui after reset xx11 1111b note: 1. when values are written to registers idb0 and idb1 , these values are transferred to the three-phase output shift regist ers by a transfer trigger. the value written in the idb0 register becomes the initial output level of each phase when the transfer trig ger occurs. the value written in the idb1 register bec omes the next output signal level when the fa lling edge of the timer a1, a2 and a4 one-shot pulses is detected. dubi dvi dvbi dwi rw rw rw rw dwbi rw ? (b7-b6) ? rw b7 b6 b5 b4 b1 b2 b3 b0 bit name upper arm (u-phase) output buffer i upper arm (v-phase) output buffer i lower arm (v-phase) output buffer i upper arm (w-phase) output buffer i function set output levels of the three-phase output shift registers. the set value is reflected in each turn-on signal as follows: 0: active (on) 1: inactive (off) when read, the contents of the three-phase output shift registers are returned. unimplemented. write 0. read as undefined value. lower arm (u-phase) output buffer i lower arm (w-phase) output buffer i m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 188 of 352 rej09b0385-0100 figure 16.10 tabsr register when using three-phase motor control timer function table 16.2 pin settings when using three-phase control timer function (1) notes: 1. set these registers after setting the inv02 bit in the invc0 register to 1 (three-phase motor control timer function used). 2. set registers ps1 and ps2 after setting other registers. port function bit setting psc register psl1, psl2, registers ps1, ps2 registers (2) p7_2 v psc_2 = 1 psl1_2 = 0 ps1_2 = 1 p7_3 v ? psl1_3 = 1 ps1_3 = 1 p7_4 w ? psl1_4 = 1 ps1_4 = 1 p7_5 w ? psl1_5 = 0 ps1_5 = 1 p8_0 u ? psl2_0 = 1 ps2_0 = 1 p8_1 u ? psl2_1 = 0 ps2_1 = 1 b7 b6 b5 b4 b1 b2 b3 symbol tabsr address 0340h after reset 00h b0 function bit symbol bit name rw tb0s tb2s timer a3 count start bit timer b2 count start bit rw rw rw rw ta4s rw ta3s timer b0 count start bit timer b1 count start bit tb1s count start register timer a4 count start bit timer a1 count start bit ta1s rw timer a2 count start bit rw ta2s 0: count stops 1: count starts timer a0 count start bit ta0s rw 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts 0: count stops 1: count starts m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 189 of 352 rej09b0385-0100 16.1 triangular wave modulation mode in triangular wave modulation mode, one cycle of carrier waveform consists of two timer b2 underflow cycles. a timer ai one-shot pulse (i = 1, 2, and 4) is generated by using a timer b2 underflow signal as a trigger. two of the timer ai one-shot pulses are used to output one cy cle of the pwm waveform. ta ble 16.3 lists specifications and settings of triangular wave modulation mode. triangular wave modulation mode has two operation modes, three-phase mode 0 and three-phase mode 1. tai register is used in three-phase mode 0. every time a timer b2 underflow interrupt occurs, the one-shot pulse width is set in the tai register. registers tai and tai1 are used in three-phase mode 1. two different widths of the one-shot pulse can be set in these registers. if a setting value of the ictb2 register is n, a timer b2 underflow interrupt is generated every n-th or every 2n-th timer b2 underflow to set values in registers tai and tai1. table 16.3 specifications and settings of triangular wave modulation mode ? : can be either 0 or 1. m: value of the tb2 register a 2k-1 : value set to the tai register at odd-numbered time. a 2k : value set to the tai register at even-numbered time. b k : value set to the tai1 register at k-th time. a k : value set to the tai register at k-th time. j: the number of interrupts item three-phase mode 0 three-phase mode 1 inv06 bit 0 0 inv11 bit 0 1 bits inv01 and inv00 00b or 01b 00b 10b 11b pwcon bit 0 0 or 1 ictb2 register 1 n carrier wave cycle upper arm active level output width inv13 bit ? indicates the timer a1 reload control signal state. timer b2 interrupt generation timing timer b2 underflow every nth timer b2 underflow every 2nth timer b2 underflow every odd-numbered (2n j - 1) timer b2 underflow every even- numbered (2n j) timer b2 underflow timer b2 reload timing timer b2 underflow ? timer b2 underflow (pwcon = 0) ? timer b2 underflow at the rising edge of the timer a1 reload control signal (pwcon = 1) transfer timing from idbp register to three-phase output shift register when a value is written to the idbp register (p = 0, 1), the value is transferred only once by the first transfer trigger. dead time timer start timing ? at the falling edge of the one-shot pulse of timer a1, a2 and a4 (inv16 = 0) ? at the rising edge of the three-phase output shift register (inv16 = 1) 2 f1 (m + 1) 2 f1 (m+1) (m+1 - a 2k-1 +a 2k ) 1 f1 1 f1 (m+1 - b k +a k ) m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 190 of 352 rej09b0385-0100 figure 16.11 shows an example of the triangular wave modulation operation (three-phase mode 0). figures 16.12 and 16.13 show examples of the triangular wa ve modulation operation (three-phase mode 1). figure 16.11 triangular wave modulati on operation (three-phase mode 0) dead time dub0 = 0 triangular waveform as a car rier wave (three-phase mode 0) carrier wave tb2s bit in the tabsr register signal wave timer b2 note: 1. internal signals. see three-phase motor control timer function block diagram. the above applies under the following conditions: - invc0 register: inv01 bit = 0 (ictb2 counter is incremented by 1 when timer b2 underflows) inv02 bit = 1 (three-phase control timer function used) inv03 bit = 1 (three-phase control timer output enabled) inv06 bit = 0 (triangular wave modulation mode) - invc1 register: inv10 bit = 0 (timer b2 underflow) inv11 bit = 0 (timers a11, a21, a41 not used (three-phase mode 0)) inv15 bit = 0 (dead time enabled) inv16 bit = 1 (rising edge o f the three-phase output shift regi ster (u-, v-, w-phase)) - ictb2 register = 01h (timer b2 interrupt is generated every t imer b2 underflow) timer a4 start trigger signal (1) ta4 register reload register (1) timer a4 one-shot pulse (1) inv14 bit in invc1 register = 0 (active low) dead time values are transferred to the three-phase output shift register from registers idb0 and idb1 rewrite registers idb0 and idb1 upper arm (u-phase) output signal (1) lower arm (u-phase) output signal (1) u-phase u-phase inv14 bit in invc1 register = 1 (active high) u-phase u-phase ir bit in the tb2ic register a 1 a 2 the following shows examples to change pwm output levels. - default value of the timer: ta4 = a 1 (the ta4 register is rewritten every time the timer b2 interrup t occurs.) first time ta4 = a 2 , second time ta4 = a 3 , third time ta4 = a 4 , fourth time ta4 = a 5 , fifth time ta4 = a 6 - default value of the registers idb0 and idb1: du0 = 1, dub0 = 0, du1 = 0, and dub1 = 1 they are changed to du0 = 1, dub0 = 0, du1 = 1, and dub1 = 0 at the sixth timer b2 interrupt. a 3 a 4 a 5 a 7 a 8 du0 = 1 du1 = 0 dub1 = 1 dub1 = 0 dub0 = 0 du0 = 1 du1 = 1 set to 0 by an interrupt request acknowledgement or by program a 2 a 1 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 2 a 1 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 6 m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 191 of 352 rej09b0385-0100 figure 16.12 triangular wave modulation operati on (three-phase mode 1)(inv01 and inv00 = 10b) dead time dub0 = 0 a 1 b 1 triangular waveform as a carri er wave (three-phase mode 1: inv0 1 and inv00 = 10b) carrier wave tb2s bit in the tabsr register signal wave timer b2 timer a4 start trigger signal (1) ta4 register reload register (1) b 2 a 2 b 3 a 3 b 4 a 4 timer a4 one-shot pulse (1) inv14 bit in invc1 register = 0 (active low) dead time values are transferred to the three-phase output shift register from registers idb0 and idb1 rewrite registers idb0 and idb1 upper arm (u-phase) output signal (1) lower arm (u-phase) output signal (1) u-phase u-phase inv14 bit in invc1 register = 1 (active high) u-phase u-phase ir bit in the tb2ic register b 1 a 1 b 2 a 2 b 3 a 3 b 4 a 4 du0 = 1 du1 = 0 dub1 = 1 dub1 = 0 dub0 = 0 du0 = 1 du1 = 1 set to 0 by an interrupt reques t acknowledgement or by program inv13 bit in the invc1 register ta41 register b 5 note: 1. internal signals. see three-phase motor control timer function block diagram. the above applies under the following conditions: - invc0 register: bits inv01 and inv00 = 10b (ictb2 counter is i ncremented by 1 at the rising edge of the timer a1 reload contr ol signal) inv02 bit = 1 (three-phase control timer function used) inv03 bit = 1 (three-phase control timer output enabled) inv06 bit = 0 (triangular wave modulation mode) - invc1 register: inv10 bit = 0 (timer b2 underflow) inv11 bit = 1 (timer a11, t21, a41 used (three-phase mode 1)) inv15 bit = 0 (dead time enabled) inv16 bit = 1 (rising edge o f the three-phase output shift regi ster (u-, v-, w-phase)) - ictb2 register = 01h (first ti mer b2 interrupt occurs when ti mer b2 underflows for the first time, and the subsequent interrupts occur every second timer b2 underflow.) the following shows examples to change pwm output levels. - default value of the timer: ta41 = b 1 , ta4 = a 1 (registers ta4 and ta41 are rewritten every time the timer b2 interrupt occurs.) first time ta41 = b 2 , ta4 = a 2 , second time ta41 = b 3 , ta4 = a 3 - default value of the registers idb0 and idb1: du0 = 1, dub0 = 0, du1 = 0, and dub1 = 1 they are changed to du0 = 1, dub0 = 0, du1 = 1, and dub1 = 0 at the third timer b2 interrupt. a 1 a 2 a 3 a 4 a 5 b 1 b 2 b 3 b 4 b 5 m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 192 of 352 rej09b0385-0100 figure 16.13 triangular wave modu lation operation (three-phase mode 1)(inv01 and inv00 = 11b) dead time dub0 = 0 triangular waveform as a carri er wave (three-phase mode 1: inv0 and inv00 = 11b) carrier wave tb2s bit in the tabsr register signal wave timer b2 timer a4 start trigger signal (1) ta4 register reload register (1) timer a4 one-shot pulse (1) inv14 bit in invc1 register = 0 (active low) dead time values are transferred to the three-phase output shift register from registers idb0 and idb1 rewrite registers idb0 and idb1 upper arm (u-phase) output signal (1) lower arm (u-phase) output signal (1) u-phase u-phase inv14 bit in invc1 register = 1 (active high) u-phase u-phase ir bit in the tb2ic register b 1 a 1 b 2 a 2 b 3 b 4 a 4 du0 = 1 du1 = 0 dub1 = 1 dub1 = 0 dub0 = 0 du0 = 1 du1 = 1 set to 0 by an interrupt reques t acknowledgement or by program inv13 bit in the invc1 register ta41 register note: 1. internal signals. see three-phase motor control timer function block diagram. the above applies under the following conditions: - invc0 register: bits inv01 and inv00 = 11b (ictb2 counter is i ncremented by 1 at the falling edge of the timer a1 reload cont rol signal) inv02 bit = 1 (three-phase control timer function used) inv03 bit = 1 (three-phase control timer output enabled) inv06 bit = 0 (triangular wave modulation mode) - invc1 register: inv10 bit = 0 (timer b2 underflow) inv11 bit = 1 (timers a11, a21, a41 used (three-phase mode 1)) inv15 bit = 0 (dead time enabled) inv16 bit = 1 (rising edge o f the three-phase output shift regi ster (u-, v-, w-phase)) - ictb2 register = 01h (every second timer b2 underflow.) (ictb2 register = 02h, if inv01 bit = 0) the following shows examples to change pwm output levels. - default value of the timer: ta41 = b 1 , ta4 = a 1 (registers ta4 and ta41 are rewritten every time the timer b2 interrupt occurs.) first time ta41 = b 2 , ta4 = a 2 , second time ta41 = b 3 , ta4 = a 3 - default value of the registers idb0 and idb1: du0 = 1, dub0 = 0, du1 = 0, and dub1 = 1 they are changed to du0 = 1, dub0 = 0, du1 = 1, and dub1 = 0 at the third timer b2 interrupt. b 3 a 1 b 1 a 1 a 2 a 3 a 4 b 1 a 2 b 2 b 3 a 3 a 5 b 1 b 2 b 3 b 4 b 5 b 2 b 4 a 4 b 4 b 5 a 3 m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 193 of 352 rej09b0385-0100 16.2 sawtooth wave modulation mode in sawtooth wave modulation mode, one cycle of carrier waveform consists of one timer b2 underflow cycle. a timer ai one-shot pulse (i = 1, 2, and 4) is generated by using a timer b2 underflow signal as a trigger. one timer ai one-shot pulse is used to output one cycle of the pwm waveform. table 16.4 lists specifications and settings of sawtooth wave modulation mode. table 16.4 specifications and settings of sawtooth wave modulation mode m: value of the tb2 register a k : value set to the tai register at k-th time. item three-phase mode 0 inv06 bit 1 inv11 bit 0 bits inv01 and inv00 00b or 01b pwcon bit 0 ictb2 register n inv16 bit 0 carrier wave cycle upper arm active level output width timer b2 interrupt generation timing every n-th timer b2 underflow timer b2 reload timing timer b2 underflow transfer timing from idbp register to three-phase output shift register (p = 0, 1) every time a transfer trigger occurs. dead time timer start timing at the falling edge of the one-shot pulse of timer a1, a2 and a4 1 f1 (m + 1) a k 1 f1 m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 194 of 352 rej09b0385-0100 figure 16.14 shows an example of the sawtooth wave modulation operation. figure 16.14 sawtooth wave modulation operation dead time dub0 = 1 sawtooth waveform as a carrier wave carrier wave tb2s bit in the tabsr register signal wave timer b2 timer a4 start trigger signal (1) ta4 register inv14 bit in invc1 register = 0 (active low) dead time values are transferred to the three-phase output shift register from registers idb0 and idb1 rewrite registers idb0 and idb1 upper arm (u-phase) output signal (1) lower arm (u-phase) output signal (1) u-phase u-phase inv14 bit in invc1 register = 1 (active high) u-phase u-phase ir bit in the tb2ic register du0 = 1 dub1 = 1 dub1 = 1 dub0 = 0 du0 = 0 du1 = 1 set to 0 by an interrupt reques t acknowledgement or by program a 2 a 1 a 4 a 3 a 6 a 5 a 8 a 7 timer a4 one-shot pulse (1) du1 = 1 note: 1. internal signals. see three-phase motor control timer function block diagram. the above applies under the following conditions: - invc0 register: inv01 bit = 0 (ictb2 counter is incremented by 1 when timer b2 underflows) inv02 bit = 1 (three-phase control timer function used) inv03 bit = 1 (three-phase control timer output enabled) inv06 bit = 1 (sawtooth wave modulation mode) - invc1 register: inv10 bit = 0 (timer b2 underflow) inv11 bit = 0 (timers a11, a21, a41 not used (three-phase mode 0)) inv15 bit = 0 (dead time enabled) inv16 bit = 0 (falling edge of one-shot pulse of timers a1, a2, and a4) - ictb2 register = 01h (timer b2 interrupt is generated every t imer b2 underflow) - tb2sc register: pwcon bit = 0 (timer b2 underflow) the following shows examples to change pwm output levels. - default value of the timer: ta4 = a 1 (the ta4 register is changed every time the timer b2 interrupt occurs.) first time ta4 = a 2 , second time ta4 = a 3 , third time ta4 = a 4 , fourth time = a 5 - default value of the registers idb0 and idb1: du0 = 0, dub0 = 1, du1 = 1, and dub1 = 1 they are changed to du0 = 1, dub0 = 0, du1 = 1, and dub1 = 1 at the fourth timer b2 interrupt. a 2 a 1 a 3 a 4 a 5 a 6 a 7 a 8 m32c/8a group 16. three-phase motor control timer function rev.1.00 jul 15, 2007 page 195 of 352 rej09b0385-0100 16.3 short circuit prevention features 16.3.1 prevention against upper/lower ar m short circuit by program errors this function prevents the upper and lower arm short circuit caused by setting the upper and lower output buffers in registers idb0 and idb1 to active simultaneously by program errors and so on. to use this function, set the inv04 bit in the invc0 regi ster to 1 (simultaneous turn-on signal output disabled). if any pair of output buffers (u and u , v and v , or w and w ) are simultaneously set to active, the inv05 bit becomes 1 (detected), and the inv03 bit becomes 0 (three -phase motor control timer output disabled). then, the port outputs are forcibly cutoff and the pins are pl aced in the high-impedance states. when this prevention function is performed, set the registers associated w ith the three-phase motor c ontrol timer function again. 16.3.2 arm short circui t prevention using dead time timer the dead time timer prevents arm short circuit caused by turn-off delay of external upper and lower transistors. to enable the dead time timer, set the inv15 bit in th e invc1 register to 0 (dead time enabled). the count source for dead time timer (fdt) can be selected using the inv12 bit, a nd the dead time can be set using the dtt register. the dead time is obtained fr om the following formulas. figure 16.15 shows an example of dead time timer operation. figure 16.15 dead time timer operation 16.3.3 forced-cutoff function by the nmi input when an ?l? signal is input to the nmi pin, the inv03 bit in the invc0 register becomes 0 (three-phase motor control timer output disabled), the port outputs are forc ibly cutoff, and then the pi ns are placed in the high- impedance states. also, the nmi interrupt occurs at the same time. to enable the three-phase motor cont rol timer function after the forced cu toff is performed, set the registers associated with the three- phase motor control timer function again wh ile an ?h? signal is input to the nmi pin. forced-cutoff function by the nmi input can be used when the inv02 b it in the invc0 register is set to 1 (three-phase motor control timer function used) and the i nv03 bit is set to 1 (three-phase motor control timer output enabled). 1 n (inv12 = 0) f1 2 n (inv12 = 1) n: value in the dtt register f1 u-phase output signal (internal signal) u-phase output signal (internal signal) dead time timer u-phase turn-on signal output u-phase turn-on signal output off off off on on on on off off off on on dead timer dead time m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 196 of 352 rej09b0385-0100 17. serial interfaces serial interfaces consist of five channels (uart0 to uart4). each uarti (i = 0 to 4) has an exclusive timer to generate the serial clock and operates independently of each other. uarti has the following modes. ? clock synchronous mode ? clock asynchronous mode ? special mode 1 (i 2 c mode) ? special mode 2 ? special mode 3 (clock-divided synchronous function, gci mode) ? special mode 4 (sim mode) ? special mode 5 (bus conflict de tect function, ie mode) (optional) (1) note: 1. please contact a renesa s sales office for optional features. m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 197 of 352 rej09b0385-0100 17.1 uart0 to uart4 figure 17.1 shows a uart0 to uart4 block diagram. fi gures 17.2 to 17.10 show the registers associated with uart0 to uart4. refer to the tables listin g for register and pin settings in each mode. figure 17.1 uart0 to uart 4 block diagram m = setting value of the uibrg register notes: 1. bits cnt3 to cnt0 in the tcspr register select no divis ion (n = 0) or divide-by-2n (n = 1 to 15). 2. select either input/output port (clki input) or clki ou tput in the function select registers. (refer to programmable i/o port .) 3. select either input/output port or rtsi output in the f unction select registers. (refer to programmable i/o port .) logic inverse circuit + msb/lsb conversion circuit high-order bits of data bus low-order bits of data bus i = 0 to 4 sp: stop bit par: parity bit smd2 to smd0, stps, p rye, iopol, and ckdir: bits in the uimr re gister clk1 and clk0, ckpol, crd, and crs: bits in the uic0 register uiere: bit in the uic1 register uarti transmit shift register logic inverse circuit + msb/lsb conversion circuit d0 d1 d2 d3 d4 d5 d6 d7 uitb register b0 b1 b2 b3 b4 b5 b6 d8 prye 0 par stps 0 sp sp txdi uiere 0 1 error signal output circuit d8 0 0 0 0 0 0 0 d0 d1 d2 d3 d4 d5 d6 d7 uirb register 1 1 iopol 0 1 rxdi iopol 0 uarti receive shift register smd2 to smd0 b0 b1 b2 b3 b4 b5 b6 b7 100 001 101 110 b8 110 001 101 prye 0 par stps 0 sp sp 001 100 101 110 1 1 1 smd2 to smd0 b7 100 001 101 110 b8 110 001 101 001 100 101 110 txdi ckpol ctsi / rtsi 100, 101, 110 smd2 to smd0 00 01 10 f1 f8 f2n (1) clk1 and clk0 rxdi rtsi output ctsi input function select register (3) ckdir uibrg register 001 receive clock transmit clock 100, 101, 110 001 receive control circuit transmit control circuit transmit/ receive unit 1/(m+1) 1/16 1/16 1/2 polarity switching crd crs 0 1 ckdir 0 1 clki polarity switching function select register (2) clki output clki input m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 198 of 352 rej09b0385-0100 figure 17.2 u0mr to u4mr registers b7 b6 b5 b4 b1 b2 b3 symbol u0mr to u2mr u3mr, u4mr address 0368h, 02e8h, 0338h 0328h,02f8h after reset 00h 00h b0 function bit symbol bit name rw smd2 smd1 smd0 pry prye b2 b1 b0 0 0 0: serial interface disabled 0 0 1: clock synchronous mode 0 1 0: i 2 c mode 1 0 0: uart mode, 7-bit data length 1 0 1: uart mode, 8-bit data length 1 1 0: uart mode, 9-bit data length do not set to values other than the above 0: internal clock 1: external clock clock select bit parity enable bit serial interface mode select bits stps ckdir 0: 1 stop bit 1: 2 stop bits 0: parity disabled 1: parity enabled stop bit length select bit enabled when prye=1 0: odd parity 1: even parity parity select bit txd, rxd input/output polarity switch bit 0: not inverted 1: inverted iopol uarti transmit/receive mode register (i = 0 to 4) rw rw rw rw rw rw rw rw m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 199 of 352 rej09b0385-0100 figure 17.3 u0smr to u4smr registers b7 0 b6 b5 b4 b1 b2 b3 symbol u0smr to u2smr u3smr, u4smr address 0367h, 02e7h, 0337h 0327h, 02f7h after reset 00h 00h b0 function bit symbol bit name rw bbs abc iicm acse sss set to 0 reserved bit transmit start condition select bit (3) i 2 c mode select bit abscs ? (b3) 0: rising edge of serial clock 1: timer aj underflow (j = 0, 3, 4) (4) 0 : not related to rxdi 1 : synchronized with rxdi bus conflict detect sampling clock select bit (3) 0: no auto clear function 1: auto cleared when bus conflict occurs auto clear function select bit for transmit enable bit (3) clock division synchronous bit (5,6) 0: external clock not divided 1: external clock divided by 2 sclkdiv uarti special mode register (i = 0 to 4) rw rw rw rw rw rw rw rw arbitration lost detect flag control bit (1) bus busy flag (1, 2) 0: updated per bit 1: updated per byte 0: stop condition detected (bus is free) 1: start condition detected (bus is busy) 0 : other than i 2 c mode 1 : i 2 c mode notes: 1. these bits are used in i 2 c mode. 2. the bbs bit is set to 0 by writing a 0. writing a 1 has no effect. 3. these bits are used in ie mode. 4. uart0: timer a3 underflow signal, uart1: timer a4 underflow signal, uart2: timer a0 underflow signal, uart3: timer a3 underflow signal, uart4: timer a4 underflow signal. 5. the sclkdiv bit is used in gci mode. 6. refer to the note for the su1him bit in the uismr2 register. m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 200 of 352 rej09b0385-0100 figure 17.4 u0smr2 to u4smr2 registers b7 b6 b5 b4 b1 b2 b3 symbol u0smr2 to u2smr2 u3smr2, u4smr2 address 0366h, 02e6h, 0336h 0326h, 02f6h after reset 00h 00h b0 function bit symbol bit name rw swc csc iicm2 swc2 sdhi when arbitration lost is detected, 0: sdai output not stopped 1: sdai output stopped sda output auto stop bit (1) sda output stop bit (2) i 2 c mode select bit 2 stc als when start condition is detected, 0: uarti not initialized 1: uarti initialized 0: output data 1: output stopped (h i-impedance state) uarti auto initialization bit (2) 0: serial clock output from scli pin 1: scli pin is held "l" scl wait output bit 2 (1) external clock synchronous enable bit (3) 0: not synchronized with external clock 1: synchronized with external clock su1him uarti special mode regi ster 2 (i = 0 to 4) rw rw rw rw rw rw rw rw clock synchronous bit (1) scl wait output bit (2) 0: not clock synchronized 1: clock synchronized 0: no wait state/release wait states 1:scli pin is held "l" after receiving 8th bit. 0: ack/nack interrupt used 1: transmit/receive interrupt used notes: 1. these bits are used w hen the mcu is in master mode in i 2 c mode. 2. these bits are used w hen the mcu is in slave mode in i 2 c mode. 3. the external clock synchronous function can be selected wi th the combination of the su1him bit and the sclkdiv bit in t he uismr register. the su1him bit is used in gci mode. sclkdiv bit in the uismr register su1him bit in the uismr2 register external clock synchronous function select 0 0 not synchronized 0 1 same frequency as external clock 1 0 or 1 external clock divided by 2 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 201 of 352 rej09b0385-0100 figure 17.5 u0smr3 to u4smr3 registers b7 b6 b5 b4 b1 b2 b3 symbol u0smr3 to u2smr3 u3smr3, u4smr3 address 0365h, 02e5h, 0335h 0325h, 02f5h after reset 00h 00h b0 function bit symbol bit name rw dinc ckph sse dl0 dl1 0: clki is cmos output 1: clki is n-channel open drain output clock output select bit ss function enable bit (1) err nodc 0: no mode error 1: mode error occurred (3) mode error flag (1) sdai output is delayed by the following cycles. b7 b6 b5 0 0 0: no delay 0 0 1: 1-to-2 cycles of brg count source 0 1 0: 2-to-3 cycles of brg count source 0 1 1: 3-to-4 cycles of brg count source 1 0 0: 4-to-5 cycles of brg count source 1 0 1: 5-to-6 cycles of brg count source 1 1 0: 6-to-7 cycles of brg count source 1 1 1: 7-to-8 cycles of brg count source sdai digital delay set bits (4, 5) dl2 uarti special mode register 3 (i = 0 to 4) rw rw rw rw rw rw rw rw clock phase set bit (1) serial input pin set bit (1) 0: no clock delay 1: clock delay 0: pins txdi and rxdi selected (master mode) 1: pins stxdi and srxdi selected (slave mode) 0: ss function disabled 1: ss function enabled (2) notes: 1. these bits are used in special mode 2. 2. when the ss pin is set to 1, set the crd bit in the uic0 register to 1 ( cts function disabled). 3. the err bit is set to 0 by writing a 0. writing a 1 has no effect. 4. digital delay is added to a sdai output using bits dl2 to dl0 in i 2 c mode. set them to 000b (no delay) in other than i 2 c mode. 5. when the external clock is selected, sdai output is delayed by approximately 100 ns in addition. m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 202 of 352 rej09b0385-0100 figure 17.6 u0smr4 to u4smr4 registers b7 b6 b5 b4 b1 b2 b3 symbol u0smr4 to u2smr4 u3smr4, u4smr4 address 0364h, 02e4h, 0334h 0324h, 02f4h after reset 00h 00h b0 function bit symbol bit name rw stpreq rstareq stareq ackc sclhi 0: serial input/output circuit selected 1: start/stop condition generation circuit selected (4) scl, sda output select bit (1) start condition generate bit (1, 3) ackd stspsel 0: ack 1: nack ack data bit (2) 0: serial data output 1: ack data output ack data output enable bit (2) swc9 uarti special mode regi ster 4 (i = 0 to 4) rw rw rw rw rw rw rw rw restart condition generate bit (1, 3) stop condition generate bit (1, 3) 0: clear 1: start 0: clear 1: start 0: clear 1: start notes: 1. these bits are used w hen the mcu is in master mode in i 2 c mode. 2. these bits are used w hen the mcu is in slave mode in i 2 c mode. 3. when each condition generation is completed, the corre sponding bit becomes 0. when a condition generation is failed, t he bit remains as 1. 4. set the stspsel bit to 1 (start/stop condition generat ion circuit selected) after setti ng the stareq bit, rstareq bit, or stpreq bit to 1 (start). scl wait output bit 3 (1) scl output stop bit (1) 0: no wait state/release wait state 1: scli pin is held "l" after receiving 9th bit when the bus is free, 0: scli output not stopped 1: scli output stopped m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 203 of 352 rej09b0385-0100 figure 17.7 u0c0 to u4c0 registers b7 b6 b5 b4 b1 b2 b3 symbol u0c0 to u2c0 u3c0, u4c0 address 036ch, 02ech, 033ch 032ch, 02fch after reset 0000 1000b 0000 1000b b0 function bit symbol bit name rw crs clk1 clk0 nch ckpol 0: data in the transmit shift register (during transmit operation) 1: no data in the transmit shift register (transmit operation is completed) transmit shift register empty flag clk polarity select bit uibrg count source select bits (1) crd txept 0: cts function enabled 1: cts function disabled 0: transmit data output at the falling edge and receive data input at the rising edge of the serial clock 1: transmit data output at the rising edge and receive data input at the falling edge of the serial clock cts function disable bit 0: txdi/sdai and scli are cmos output ports 1: txdi/sdai and scli are n-channel open drain output ports data output select bit 3) bit order select bit (4) 0 : lsb first 1 : msb first uform uarti transmit/receive contro l register 0 (i = 0 to 4) rw rw rw ro rw rw rw rw cts function select bit enabled when crd = 0 0: cts function selected 1: cts function not selected b1 b0 0 0: f1 selected 0 1: f8 selected 1 0: f2n selected (2) 1 1: do not set to this value notes: 1. set the uibrg register after setting bits clk1 and clk0. 2. bits cnt3 to cnt0 in the tcspr register select no divi sion (n = 0) or divide-by-2n (n = 1 to 15). to select f2n, set th e cst bit in the tcspr register to 1 before setting bits clk1 and clk0 to 10b. 3. p7_0/txd2, p7_1/scl2 are n-channel open drain out put ports. they cannot be sele cted as cmos output ports. 4. the uform bit is enabled when bits smd2 to smd0 in the uimr register are set to 001b (clock synchronous mode) or 101b (uart mode, 8-bit data length). set the uform bit to 1 when bits smd2 to smd0 are set to 010b (i 2 c mode), or to 0 when bits smd2 to smd0 are set to 100b (uart mode, 7-bit data length) or 110b (uart mode, 9-bit data length). m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 204 of 352 rej09b0385-0100 figure 17.8 u0brg to u4brg regist ers, u0c1 to u4c1 registers b7 b6 b5 b4 b1 b2 b3 symbol u0c1 to u2c1 u3c1, u4c1 address 036dh, 02edh, 033dh 032dh, 02fdh after reset 0000 0010b 0000 0010b b0 function bit symbol bit name rw re ti te uirrm uilch 0: no data in the uirb register 1: data in the uirb register receive complete flag data logic select bit (1) transmit enable bit uilrs ri 0: no data in the uitb register (ti = 1) 1: transmit operation is completed (txept = 1) 0: not inverted 1: inverted uarti transmit interrupt source select bit 0: continuous receive mode disabled 1: continuous receive mode enabled (3) continuous receive mode enable bit special mode 3 clock-divided synchronous stop bit special mode 4 error signal output enable bit (2) 0: synchronization stopped 1: synchronization started 0: not output 1: output sclkstpb uiere uarti transmit/receive contro l register 1 (i = 0 to 4) rw ro rw ro rw rw rw rw receive enable bit 0: receive operation disabled 1: receive operation enabled 0: transmit operation disabled 1: transmit operation enabled notes: 1. the uilch bit is enabled when bits smd2 to smd0 in the uimr register are set to 001b (clock synchronous mode), 100b (uart mode, 7-bit data length), or 101b (uart mode, 8-bit data length). set the uilch bit to 0 when bits smd2 to smd0 are set to 010b (i 2 c mode) or 110b (uart mode, 9-bit data length). 2. set bits smd2 to smd0 before setting the uiere bit. 3. when the uirrm bit is set to 1, set the ckdir bit in the uimr register to 1 (external clock) and also disable the rts f unction. uitb register empty flag 0: data in the uitb register 1: no data in the uitb register 0 b7 symbol u0brg to u2brg u3brg, u4brg address 0369h, 02e9h, 0339h 0329h, 02f9h after reset undefined undefined b0 function rw if the setting value is n , the uibrg register divides a count source by n +1 00h to ffh uarti baud rate register (1, 2) (i = 0 to 4) wo setting range notes: 1. read-modify-write instructions cannot be used to set the uibrg register. refer to usage notes for details. 2. set the uibrg register after setting bits clk1 and clk0 in the uic0 register. m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 205 of 352 rej09b0385-0100 figure 17.9 ifsr register b7 b6 b5 b4 b1 b2 b3 external interrupt source select register symbol ifsr address 031fh bit symbol bit name rw after reset 00h b0 function ifsr0 rw 0: one edge 1: both edges int0 interrupt polarity select bit (1) ifsr1 int1 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr2 int2 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr3 int3 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr4 int4 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr5 int5 interrupt polarity select bit (1) 0: one edge 1: both edges ifsr6 uart0, uart3 interrupt source select bit 0: uart3 bus conflict, start condition detection, stop condition detection 1: uart0 bus conflict, start condition detection, stop condition detection rw rw rw rw rw rw ifsr7 uart1, uart4 interrupt source select bit 0: uart4 bus conflict, start condition detection, stop condition detection 1: uart1 bus conflict, start condition detection, stop condition detection rw note: 1. set the ifsri bit (i = 0 to 5) to 0 to select a level-sensitive triggering. when selecting both edges, set the pol bit in the corresponding intilc register to 0 (falling edge). m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 206 of 352 rej09b0385-0100 figure 17.10 u0tb to u4tb registers, u0rb to u4rb registers symbol address after reset rw wo uarti transmit buffer register (1) (i = 0 to 4) u0tb to u2tb u3tb, u4tb 036bh - 036ah, 02ebh - 02eah, 033bh - 033ah 032bh - 032ah, 02fbh - 02fah undefined undefined function bit symbol transmit data (d7 to d0) b7 b8 b15 b0 ? (b7-b0) wo transmit data (d8) ? (b8) ? unimplemented. write 0. read as undefined value. ? (b15-b9) symbol address after reset rw ro uarti receive buffer register (i = 0 to 4) u0rb to u2rb u3rb, u4rb 036fh - 036eh, 02efh - 02eeh, 033fh - 033eh 032fh - 032eh, 02ffh - 02feh undefined undefined function bit symbol received data (d7 to d0) b7 b8 b15 b0 ? (b7-b0) ro received data (d8) ? (b8) ? ? (b10-b9) note: 1. read-modify-write instructions cannot be used to set the uitb register. refer to usage notes for details. bit name unimplemented. write 0. read as undefined value. rw 0: not detected (won) 1: detected (lost) arbitration lost detect flag (1) abt ro 0: no overrun error 1: overrun error overrun error flag (2) oer ro 0: no framing error 1: framing error framing error flag (2, 3) fer ro 0: no parity error 1: parity error parity error flag (2, 3) per ro 0 no error occurred 1: error occurred error sum flag (2, 3) sum notes: 1. only a 0 can be written to the abt bit. 2. when bits smd2 to smd0 in the uimr register are set to 000b (serial interface disabled) or the re bit in the uic1 regis ter is set to 0 (receive operation disabled), bits oer, fer, per and sum become 0. when all of bits oer, fer and per become 0, the sum bit also becomes 0. bits fer and per become 0 by reading the low-order byte in the uirb register. 3. bits fer, per and sum are disabled when bits smd2 to smd0 in the uimr register are set to 001b (clock synchronous mode) or 010b (i 2 c mode). a read from these bits returns undefined value. m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 207 of 352 rej09b0385-0100 17.1.1 clock synchronous mode full-duplex clock synchronous serial communications are allowed in this mode. cts/rts function can be used for transmit and receive control. table 17.1 lists specifications of clock synchronous mode . table 17.2 lists pin sett ings. figure 17.11 shows register settings. figure 17.12 shows an example of a transmit and receive operation when an internal clock is selected. figure 17.13 shows an example of a receive operation when an external clock is selected. table 17.1 clock synchronous mode specifications notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. if an external clock is selected, ensure that an ?h? signal is applied to the clki pin when the ckpol bit in the uic0 register is set to 0, and that an ?l? signal is applied when the ckpol bit is set to 1. 3. if an overrun error occurs, a read from the uirb register returns undefined values. the ir bit in the siric register remains unchanged as 0 (interrupt not requested). item specification data format data length: 8 bits long serial clock internal clock or external clock can be selected by the ckdir bit in the uimr register (i = 0 to 4) baud rate ? when the ckdir bit is set to 0 (internal clock): fj / (2 (m + 1) fj = f1, f8, f2n (1) m: setting value of the uibrg register (00h to ffh) ? when the ckdir bit is set to 1 (external clock): clock input to the clki pin transmit/receive control selectable among the cts f unction, rts function, or cts/rts function disabled transmit and receive start condition internal clock is selected: ? set the te bit in the uic1 register to 1 (transmit operation enabled) ? the ti bit in the uic1 register is 0 (data in the uitb register) ? set the re bit in the uic1 register to 1 (receive operation enabled) ? ?l? signal is applied to the ctsi pin when the cts function is used external clock is selected (2) : ? set the te bit to 1 ? the ti bit is 0 ? set the re bit to 1 ? the ri bit in the uic1 register is 0 when the rts function is used when above 4 conditions are met, rtsi pin outputs ?l? if transmit-only operation is performed, the re bit setting is not required in both cases. interrupt request generation timing transmit interrupt (the uiirs bit in the uic1 register selects one of the following): ? the uiirs bit is set to 0 (no data in the uitb register): when data is transferred from the uitb register to the uarti transmit shift register (transmit operation started) ? the uiirs bit is set to 1 (transmit operation completed): when data transmit operation from the uarti transmit shift register is completed receive interrupt: ? when data is transferred from the uarti receive shift register to the uirb register (receive operation completed) error detection overrun error (3) overrun error occurs when the 7th bit of the next data is received before reading the uirb register selectable function ? clk polarity transmit data output timing and receive data input timing can be selected ? lsb first or msb first data is transmitted and received from either bit 0 or bit 7 ? serial data logic inverse transmit and receive data are logically inverted ? continuous receive mode the ti bit becomes 0 by reading the uirb register m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 208 of 352 rej09b0385-0100 table 17.2 pin settings in clock synchronous mode notes: 1. set registers ps0, ps1, and ps3 after setting other registers. 2. set the pd9 or ps3 register immediately after the prc2 bi t in the prcr register is set to 1 (write enable). do not generate an interrupt or a dma or dmacii transfer between these two instructions. 3. p7_0 is an n-channel open drain output port. 4. after uarti (i = 0 to 4) operating mode is selected and the pin function is set in the function select registers, the txdi pin outputs an ?h? signal until a transmit operatio n starts (the txdi pin is in a high-impedance state when n-channel open drain output is selected). port function bit setting pd6, pd7, pd9 registers (2) psc register psl0, psl1, psl3 registers ps0, ps1, ps3 registers (1)(2) p6_0 cts0 input pd6_0 = 0 ?? ps0_0 = 0 rts0 output ?? psl0_0 = 0 ps0_0 = 1 p6_1 clk0 input pd6_1 = 0 ?? ps0_1 = 0 clk0 output ? ? psl0_1 = 0 ps0_1 = 1 p6_2 rxd0 input pd6_2 = 0 ?? ps0_2 = 0 p6_3 txd0 output (4) ? ? psl0_3 = 0 ps0_3 = 1 p6_4 cts1 input pd6_4 = 0 ?? ps0_4 = 0 rts1 output ?? psl0_4 = 0 ps0_4 = 1 p6_5 clk1 input pd6_5 = 0 ?? ps0_5 = 0 clk1 output ?? psl0_5 = 0 ps0_5 = 1 p6_6 rxd1 input pd6_6 = 0 ?? ps0_6 = 0 p6_7 txd1 output (4) ?? psl0_7 = 0 ps0_7 = 1 p7_0 (3) txd2 output (4) ? psc_0 = 0 psl1_0 = 0 ps1_0 = 1 p7_1 rxd2 input pd7_1 = 0 ?? ps1_1 = 0 p7_2 clk2 input pd7_2 = 0 ?? ps1_2 = 0 clk2 output ? psc_2 = 0 psl1_2 = 0 ps1_2 = 1 p7_3 cts2 input pd7_3 = 0 ?? ps1_3 = 0 rts2 output ? psc_3 = 0 psl1_3 = 0 ps1_3 = 1 p9_0 clk3 input pd9_0 = 0 ?? ps3_0 = 0 clk3 output ?? psl3_0 = 0 ps3_0 = 1 p9_1 rxd3 input pd9_1 = 0 ?? ps3_1 = 0 p9_2 txd3 output (4) ?? psl3_2 = 0 ps3_2 = 1 p9_3 cts3 input pd9_3 = 0 ? psl3_3 = 0 ps3_3 = 0 rts3 output ?? ? ps3_3 = 1 p9_4 cts4 input pd9_4 = 0 ? psl3_4 = 0 ps3_4 = 0 rts4 output - ? ? ps3_4 = 1 p9_5 clk4 input pd9_5 = 0 ? psl3_5 = 0 ps3_5 = 0 clk4 output ??? ps3_5 = 1 p9_6 txd4 output (4) ??? ps3_6 = 1 p9_7 rxd4 input pd9_7 = 0 ?? ps3_7 = 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 209 of 352 rej09b0385-0100 figure 17.11 register settings in clock synchronous mode i = 0 to 4 notes: 1. bits cnt3 to cnt0 in the tcspr register select no divis ion (n = 0) or divide-by-2n (n = 1 to 15). 2. the uirrm bit can be set to 1 (continuous receive mode used), only when the ckdir bit in the uimr register is set to 1 (external clock) and rts function is disabled. clock synchronous mode clock select bit uibrg register count source select bits cts function select bit cts function disable bit data output select bit clk polarity select bit bit order select bit m = 00h to ffh baud rate = transmit operation disabled receive operation disabled uarti transmit interrupt source select bit continuous receive mode enable bit (2) data logic select bit fj 2(m + 1) fj: f1, f8, f2n (1) m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 210 of 352 rej09b0385-0100 figure 17.12 transmit and receive operations when internal clock is selected transfer data from uarti receive shift register to uirb register communication stops because te bit = 0 communication stops because ctsi = "h" d7 te bit in the uic1 register i = 0 to 4 the above applies under the following conditions: - uimr register: ckdir bit = 0 (internal clock) - uic0 register: crd bit in the = 0 and crs bit = 0 (cts f unction used) ckpol bit = 0 (transmit data output at the falling edge of the serial clock) - uic1 register: u iirs bit = 0 (transm it interrupt request is generated when no data in the uitb register) note: 1. bits cnt3 to cnt0 in the tcspr register select no divis ion (n = 0) or divide-by-2n (n = 1 to 15). tc 1 0 internal clock ti bit in the uic1 register write data to the uitb register ctsi input h l clki output tclk txdi output d0 txep bit in the uic0 register ir bit in the sitic register 2(m + 1) fj tc = tclk = fj = f1, f8, f2n (1) m = setting value of the uibrg register (00h to ffh) d1 d2 d3 d4 d5 d6 h l h l d7 d0 d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 transfer data from uitb register to uarti transmit shift register d7 rxdi input d0 d1 d2 d3 d4 d5 d6 h l d7 d0 d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 set to 0 by an interrupt request acknowledgement or by program ri bit in the uic1 register ir bit in the siric register a read from the uirb register set to 0 by an interrupt request acknowlegement or by program 1 0 1 0 1 0 1 0 1 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 211 of 352 rej09b0385-0100 figure 17.13 receive operations when external clock is selected d6 d7 d7 te bit in the uic1 register i = 0 to 4 fext = external clock frequency the above applies under the following conditions: - uimr register: ckdir bit = 1 (external clock) - uic0 reigster: crd bit = 1 (cts function disabled) ckpol bit = 0 (receive data inpu t at the rising edge of the ser ial clock) note: 1. satisfy the following condi tions, while the clki pin in put is "h" before the data receive operation. - uic1 register: te bi t = 1 (transmit operation enabl ed) re bit = 1 (receive operation enabled) - write dummy data to the uitb register ti bit in the uic1 register write dummy data to uitb register rtsi output h l clki input (1) rxdi input ri bit in the uic1 register ir bit in the siric register set to 0 by an interrupt request acknowledgement or by program re bit in the uic1 register 1 0 oer bit in the uirb register 1 fext d0 d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 d7 h l h l transfer data from uitb register to uarti transmit shift register becomes "l" by reading uirb register transfer data from uarti receive shift register to uirb register a read from uirb register 1 0 1 0 1 0 1 0 1 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 212 of 352 rej09b0385-0100 17.1.1.1 clk polarity as shown in figure 17.14, the ckpol bit in the uic0 register (i = 0 to 4) determines the polarity of the serial clock. figure 17.14 serial clock polarity clki (1) when the ckpol bit in the uic 0 register (i = 0 to 4) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the s erial clock ) d0 d1 d3 d4 d5 d6 d7 d2 d0 d1 d3 d4 d5 d6 d7 d2 d0 d1 d3 d4 d5 d6 d7 d2 d0 d1 d3 d4 d5 d6 d7 d2 (2) when the ckpol bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock) txdi rxdi the above applies under the following conditions: - uform bit in the uic0 register is set to 0 (lsb first) - uilch bit in the uic1 register is set to 0 (not inverted ). notes: 1. the clki pin output level is "h" when no transmit and receive operation is in progress. 2. the clki pin output level is "l" when no transmit and receive operation is in progress. "h" "l" "h" "l" "h" "l" clki txdi rxdi "h" "l" "h" "l" "h" "l" (note 1) (note 2) m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 213 of 352 rej09b0385-0100 17.1.1.2 lsb first or msb first as shown in figure 17.15, the uform bit in the uic0 register (i = 0 to 4) determines a bit order. figure 17.15 bit order (8-bit data length) (1) when the uform bit in the uic0 register (i = 0 to 4) is set to 0 (lsb first) the above applies under the following conditions: - ckpol bit in the uic0 register is set to 0 (transmit data is output at the falling edge and received data is input at t he rising edge) - uilch bit in the uic1 register is set to 0 (not inverted). d0 d1 d3 d4 d5 d6 d7 d2 d0 d1 d3 d4 d5 d6 d7 d2 d0 d1 d3 d4 d5 d6 d7 d2 (2) when the uform bit is set to 1 (msb first) d0 d1 d3 d4 d5 d6 d7 d2 clki txdi rxdi "h" "l" "h" "l" "h" "l" clki txdi rxdi "h" "l" "h" "l" "h" "l" m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 214 of 352 rej09b0385-0100 17.1.1.3 serial data logic inverse when the uilch bit in the uic1 register is set to 1 (inverted), data logic written in the uitb register is inverted for transmit operation. a re ad from the uirb register re turns the inverted logic of receive data. figure 17.16 shows an example of serial data logic inverse operation. figure 17.16 serial data logic inverse serial clock (1) when the uilch bit in the uic1 register (i = 0 to 4) is set to 0 (not inverted) d0 d1 d3 d4 d5 d6 d7 d2 (2) when the uilch bit is set to 1 (inverted) txdi (not inverted) the above applies under the following conditions: - ckpol bit in the uic0 register is set to 0 (transmit data is output at the falling edge and received data is input at th e rising edge) - uform bit in the uic0 register is set to 0 (lsb first). "h" "l" "h" "l" d0 d1 d3 d4 d5 d6 d7 d2 serial clock txdi (inverted) "h" "l" "h" "l" d0 d1 d3 d4 d5 d6 d7 d2 rxdi (not inverted) "h" "l" d0 d1 d3 d4 d5 d6 d7 d2 rxdi (inverted) "h" "l" m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 215 of 352 rej09b0385-0100 17.1.1.4 continuous receive mode continuous receive mode can be used when all of the following conditions are met. ? external clock is selected (t he ckdir bit in the uimr register (i = 0 to 4) is set to 1) ? rts function is disabled (rtsi pin is not selected in the function select register) when the uirrm bit in the uic1 register is set to 1 (c ontinuous receive mode enable d), the ti bit in the uic1 register becomes 0 (data in the uitb register) by reading the uirb register. do not set dummy data to the uitb register if the uirrm bit is set to 1. 17.1.1.5 cts/rts function ? cts function transmit and receive operation is controlled by using the input signal to the ctsi pin (i = 0 to 4). to use the cts function, select the i/o port in the function se lect register, set the crd bit in the uic0 register to 0 (cts function enabled), and the crs bit to 0 (cts function selected). with the cts function used, the tran smit and receive operation starts when all the following conditions are met and an ?l? signal is applied to the ctsi pin. -the te bit in the uic1 register is set to 1 (transmit operation enabled) -the ti bit in the uic1 regi ster is 0 (data in the uitb register) -the re bit in the uic1 regist er is set to 1 (receive operation enabled) (if transmit-only operation is perf ormed, the re bit setting is not required) when a high-level (?h?) signal is applied to the ctsi pin during transmitting and receiving, the transmit and receive operation is disabled after the transmit and receive ope ration in progress is completed. ? rts function the mcu can inform the external device that it is ready for a transmit and rece ive operation by using the output signal from the rtsi pin. to use the rts function, select the rtsi pin in the function select register. with the rts function used, the rtsi pin outputs an ?l? signal when all the following conditions are met, and outputs an ?h? when the serial clock is input to the clki pin. -the ri bit in the uic1 register is 0 (no data in the uirb register) -the te bit is set to 1 (transmit operation enabled) -the re bit is set to 1 (receive operation enabled) (if transmit-only operation is perf ormed, the re bit setting is not required) -the ti bit is 0 (data in the uitb register) 17.1.1.6 procedure when the co mmunication error is occurred follow the procedure below when a communication error is occurred in clock synchronous mode. (1) set the te bit in the uic1 register (i = 0 to 4) to 0 (transmit operation disabled) and the re bit to 0 (receive operation disabled). (2) set bits smd2 to smd0 in the uimr register to 000b (serial interface disabled). (3) set bits smd2 to smd0 in the uimr register to 001b (clock synchronous mode). (4) set the te bit to 1 (transmit operation enabled) and the re bi t to 1 (receive operation enabled). m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 216 of 352 rej09b0385-0100 17.1.2 clock asynchronous (uart) mode full-duplex asynchronous serial communications are allowed in this mode. table 17.3 lists specifications of uart mode. table 17.4 lists pin settings. figure 17. 17 shows register settings. figure 17.18 shows an example of a transmit operatio n. figure 17.19 shows an ex ample of a receive operation. table 17.3 uart m ode specifications notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. if an overrun error occurs, a read from the uirb register returns undefined values. the ir bit in the siric register remains unchanged as 0 (interrupt not requested). item specification data format ? data length: selectable among 7 bits, 8 bits, or 9 bits long ? start bit: 1 bit long ? parity bit: selectable among odd, even, or none ? stop bit: selectable from 1 bit or 2 bits long baud rate fj / (16 (m + 1)) fj = f1, f8, f2n (1) , fext m: setting value of the uibrg register (00h to ffh) fext: clock input to the clki pin when the ckdir bit in the uimr register is set to 1 (external clock) transmit/receive control selectable among cts func tion, rts function or cts/rts function disabled transmit start condition to start transmit operation, all of the following must be met: ? set the te bit in the uic1 register to 1 (transmit operation enabled) ? the ti bit in the uic1 register is 0 (data in the uitb register) ? apply a low-level (?l?) signal to the ctsi pin when the cts function is selected receive start condition to start receive operation, all of the following must be met: ? set the re bit in the uic1 register to 1 (receive operation enabled) ? the ri bit is 1 (no data in uirb register) when rts function is used. when the above two conditions are met, the rtsi pin output an ?l? signal. ? the start bit is detected interrupt request generation timing transmit interrupt (the uiirs bit in the uic1 register selects one of the following): ? the uiirs bit is set to 0 (no data in the uitb register): when data is transferred from the uitb register to the uarti transmit shift register (transmit operation started) ? the uiirs bit is set to 1 (transmit operation completed): when the final stop bit is output from the uarti transmit shift register receive interrupt: ? when data is transferred from the uarti receive shift register to the uirb register (receive operation completed) error detection ? overrun error (2) overrun error occurs when the preceding bit of the final stop bit of the next data (the first stop bit when selecting 2 stop bits) is received before reading the uirb register ? framing error framing error occurs when the number of the stop bits set by the stps bit in the uimr register is not detected ?parity error parity error occurs when parity is enabled and the received data does not have the correct even or odd parity set by the pry bit in the uimr register. ? error sum flag error sum flag is set to 1 when any of overrun, framing, and parity errors occurs selectable function ? lsb first or msb first data is transmitted or received from either bit 0 or bit 7 ? serial data logic inverse transmit and receive data are logically inverted. the start bit and stop bit are not inverted ? txd and rxd i/o polarity inverse the level output from the txd pin and the level applied to the rxd pin are inverted. all the data including the start bit and stop bit are inverted. m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 217 of 352 rej09b0385-0100 table 17.4 pin settings in uart mode notes: 1. set registers ps0, ps1, and ps3 after setting other registers. 2. set the pd9 or ps3 register immediately after the prc2 bit in the prcr register is set to 1 (write enable). do not generate an interrupt or a dma or dmacii transfer between these two instructions. 3. p7_0 is an n-channel open drain output port. 4. after uarti (i = 0 to 4) operating mode is selected and the pin function is set in the function select registers, the txdi pin outputs an ?h? signal until a transmit operatio n starts (the txdi pin is in a high-impedance state when n-channel open drain output is selected). port function bit setting pd6, pd7, pd9 registers (2) psc register psl0, psl1, psl3 registers ps0, ps1, ps3 registers (1)(2) p6_0 cts0 input pd6_0 = 0 ?? ps0_0 = 0 rts0 output ? ? psl0_0 = 0 ps0_0 = 1 p6_1 clk0 input pd6_1 = 0 ?? ps0_1 = 0 p6_2 rxd0 input pd6_2 = 0 ?? ps0_2 = 0 p6_3 txd0 output (4) ? ? psl0_3 = 0 ps0_3 = 1 p6_4 cts1 input pd6_4 = 0 ?? ps0_4 = 0 rts1 output ? ? psl0_4 = 0 ps0_4 = 1 p6_5 clk1 input pd6_5 = 0 ?? ps0_5 = 0 p6_6 rxd1 input pd6_6 = 0 ?? ps0_6 = 0 p6_7 txd1 output (4) ? ? psl0_7 = 0 ps0_7 = 1 p7_0 (3) txd2 output (4) ? psc_0 = 0 psl1_0 = 0 ps1_0 = 1 p7_1 rxd2 input pd7_1 = 0 ?? ps1_1 = 0 p7_2 clk2 input pd7_2 = 0 ?? ps1_2 = 0 p7_3 cts2 input pd7_3 = 0 ?? ps1_3 = 0 rts2 output ? psc_3 = 0 psl1_3 = 0 ps1_3 = 1 p9_0 clk3 input pd9_0 = 0 ?? ps3_0 = 0 p9_1 rxd3 input pd9_1 = 0 ?? ps3_1 = 0 p9_2 txd3 output (4) ?? psl3_2 = 0 ps3_2 = 1 p9_3 cts3 input pd9_3 = 0 ? psl3_3 = 0 ps3_3 = 0 rts3 output ?? ? ps3_3 = 1 p9_4 cts4 input pd9_4 = 0 ? psl3_4 = 0 ps3_4 = 0 rts4 output ?? ? ps3_4 = 1 p9_5 clk4 input pd9_5 = 0 ? psl3_5 = 0 ps3_5 = 0 p9_6 txd4 output (4) ? ?? ps3_6 = 1 p9_7 rxd4 input pd9_7 = 0 ?? ps3_7 = 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 218 of 352 rej09b0385-0100 figure 17.17 register settings in uart mode i = 0 to 4 fext: clock input to the clki pin when the external clock is se lected notes: 1. set bits smd2 to smd0 to the following: 100b (7 bits lo ng), 101b (8 bits long), 110b (9 bits long). 2. a bit order can be selected when 8-bit data length is s elected. set to 0 when 7-bit or 9 -bit data lengt h is selected. 3. bits cnt3 to cnt0 in the tcspr register select no divis ion (n = 0) or divide-by-2n (n = 1 to 15). 4. whether data logic is inverted or not can be selected w hen 7-bit or 8-bit data length is s elected. set to 0 when 9-bit data length is selected. uart mode (1) select bits clock select bit stop bit length select bit parity select bit parity enable bit txd, rxd i/o polarity switch bit uibrg register count source select bits cts function select bit cts function disable bit data output select bit bit order select bit (2) transmit operation disabled receive operation disabled uarti transmit interrupt request source select bit data logic select bit (4) m = 00h to ffh baud rate = fj 16(m+1) fj = f1, f8, f2n (3) , fext pin settings in the function select registers uimr register: bits smd2 to smd0 ckdir bit stps bit pry bit prye bit iopol bit uismr register = 00h uismr2 register = 00h uismr3 register = 00h uismr4 register = 00h uibrg register = m uic1 register: te bit = 0 re bit = 0 uiirs bit uirrm bit = 0 uilch bit bit 7 = 0 transmit operation starts by writing data to the uitb register uic0 register: bits clk1 and clk0 crs bit crd bit nch bit ckpol bit = 0 uform bit start initial setting end itinial setting receive operation starts when the start bit is detected. read the uirb register when the receive operation is completed. transmit operation enabled receive operation enabled uic1 register: te bit = 1 re bit = 1 transmit interrupt priority level select bits interrupt not requested sitic register: bits ilvl2 to ilvl0 ir bit = 0 receive interrupt prior ity level select bits interrupt not requested siric register: bits ilvl2 to ilvl0 ir bit = 0 interrupt enabled i flag = 1 interrupt disabled i flag = 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 219 of 352 rej09b0385-0100 figure 17.18 transmit operation in uart mode sp sp sp sp stop bit parity bit start bit (1) example of the transmit operation timing in 8-bit data leng th (parity enabled, 1 stop bit) transmission stops because te = 0 d7 te bit in the uic1 register the above applies under the following conditions: - uimr register: prye bit = 1 (parity enabled), stps bit = 0 (1 stop bit) - uic0 register: crd bit = 0 and crs bit = 0 (cts function used) - uic1 register: uiirs bit = 1 (transmit interrupt is gene rated when the transmit operation is completed) tc 1 0 internal transmit clock ti bit in the uic1 register write data to uitb register ctsi input h l transfer data from uitb register to uarti transmit shift regist er txdi output d0 txept bit in the uic0 register ir bit in the sitic register set to 0 by an interrupt request a cknowledgement or by program d1 d2 d3 d4 d5 d6 st p d7 d0 d1 d2 d3 d4 d5 d6 st p d0 st sp sp stop bits start bit (2) example of the transmit operation timing in 9-bit data leng th (parity disabled, 2 stop bit) d7 te bit in the uic1 register the above applies under the following conditions: - uimr register: prye bit = 0 (parity disabled), stps bit = 1 (2 stop bits) - uic0 register: crd bit = 1 (cts function disabled) - uic1 register: uiirs bit = 0 (transmit interrupt is gene rated when no data in the uitb register) tc ti bit in the uic1 register write data to uitb register transfer data from uitb register to uarti transmit shift regist er txdi output d0 txept bit in the uic0 register ir bit in the sitic register set to 0 by an interrupt request acknowledgement or by program 16(m + 1) fj tc = i = 0 to 4 note: 1. bits cnt3 to cnt0 in the tcspr register select no divis ion (n = 0) or divide-by-2n (n = 1 to 15). d1 d2 d3 d4 d5 d6 st d8 d7 d0 d1 d2 d3 d4 d5 d6 st d8 d0 st internal transmit clock h l h l fj: f1, f8, f2n (1) , fext fext: clock input to the clki pin when the external clock is se lected m: setting value of the uibrg register (00h to ffh) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 220 of 352 rej09b0385-0100 figure 17.19 receive operation in uart mode rxdi input d0 start bit stop bit verify the level (note 2) clock divided by uibrg register input the receive data h l (note 1) internal receive clock ir bit in the siric register ri bit in the uic1 register 1 0 1 0 rtsi output h l i = 0 to 4 the above applies under the following conditions: - uimr register: stps bit = 0 (1 stop bit) - uic0 register: crs bit = 1 (cts function not used) notes: 1. rxdi input is sampled u sing the clock divided by the se tting value of the uibrg register. the internal receive clock is generated after detec ting the falling edge of the star t bit, and then the receive operation starts. 2. when "l" is detected, th e receive operation continues. when "h" is detected, the rec eive operation is cancelled. when the receive oper atin is cancelled, the rtsi outpu t becomes "l". example of the receiv e operation timing (1 stop bit) this bit becomes 1 when the data is transferred from uarti receive shift register to uirb register set to 0 by an interrupt request acknowledgement or by program the ri bit becomes 0 and rtsi output becomes "l" by reading the uirb register the output signal becomes "l" when the re bit in the uic1 register is set to 1 the output signal becomes "h" when the receive operation starts m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 221 of 352 rej09b0385-0100 17.1.2.1 baud rate in uart mode, the baud rate is the frequency of the clock divided by the setting value of the uibrg register (i = 0 to 4) and again divided by 16. table 17.5 lists an example of baud rate setting. table 17.5 baud rate 17.1.2.2 lsb first or msb first as shown in figure 17.20, the uform bit in the uic0 regist er (i = 0 to 4) determines a bit order. this function can be used when data length is 8 bits long. figure 17.20 bit order target baud rate (bps) uibrg count source peripheral clock: 16mhz peripheral clock: 24mhz peripheral clock: 32mhz uibrg setting value: n actual baud rate (bps) uibrg setting value: n actual baud rate (bps) uibrg setting value: n actual baud rate (bps) 1200 f8 103(67h) 1202 155(9bh) 1202 207(cfh) 1202 2400 f8 51(33h) 2404 77(4dh) 2404 103(67h) 2404 4800 f8 25(19h) 4808 38(26h) 4808 51(33h) 4808 9600 f1 103(67h) 9615 155(9bh) 9615 207(cfh) 9615 14400 f1 68(44h) 14493 103(67h) 14423 138(8ah) 14388 19200 f1 51(33h) 19231 77(4dh) 19231 103(67h) 19231 28800 f1 34(22h) 28571 51(33h) 28846 68(44h) 28986 31250 f1 31(1fh) 31250 47(2fh) 31250 63(3fh) 31250 38400 f1 25(19h) 38462 38(26h) 38462 51(33h) 38462 51200 f1 19(13h) 50000 28(1ch) 51724 38(26h) 51282 actual baud rate = uibrg register count source 16 (uibrg register setting value + 1) (1) when the uform bit in the uic0 register (i = 0 to 4) is set to 0 (lsb first) st d0 d2 d3 d4 d5 sp d1 (2) when the uform bit is set to 1 (msb first) txdi rxdi the above applies under the following conditions: - uic0 register: ckpol bit = 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock) - uic1 register: uilch bit = 0 (not inverted) and the uilch bit in the uic1 register is set to 0 (not inverted). st: start bit p: parity bit sp: stop bit d6 d7 p st d0 d2 d3 d4 d5 sp d1 d6 d7 p st d7 d5 d4 d3 d2 sp d6 txdi rxdi d1 d0 p st sp p d7 d5 d4 d3 d2 d6 d1 d0 "h" "l" "h" "l" "h" "l" "h" "l" m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 222 of 352 rej09b0385-0100 17.1.2.3 serial data logic inverse when the uilch bit in the uic1 register is set to 1 (inverted), data logic written in the uitb register is inverted for transmit operation. a read from the uirb register returns the inverted logic of receive data. this function can be used when data length is 7 bits or 8 bits long. figure 17.21 shows an example of serial data logic inverse operation. figure 17.21 serial data logic inverse 17.1.2.4 txd and rxd i/o polarity inverse the level output from the txd pin and the level applied to the rxd pin are inverted with this function. when the iopol bit in the uimr register (i = 0 to 4) is set to 1 (inverted), all the input/output data levels, including the start bit, stop bit and parity bit, are inverted . figure 17.22 shows txd and rxd i/o polarity inverse. figure 17.22 txd and rxd i/o polarity inverse (1) when the uilch bit in the uic1 register (i = 0 to 4) is set to 0 (not inverted) (2) when the uilch bit is set to 1 (inverted) txdi (not inverted) the above applies under the following conditions: - uic0 register: ufrom bit = 0 (lsb first) - uimr register: stps bit = 0 (1 stop bit) prye bit = 1 (parity enabled). "h" "l" st d0 d2 d3 d4 d5 sp d1 d6 d7 p st d0 d2 d3 d4 d5 sp d1 d6 d7 p "h" "l" txdi (inverted) (1) when the iopol bit in the uimr register (i = 0 to 4) is set to 0 (not inverted) (2) when the iopol bit is set to 1 (inverted) txdi (not inverted) the above applies under the following conditions: - uic0 register: uform bit = 0 (lsb first) - uimr register: stps bit = 0 (1 stop bit) prye bit = 1 (parity enabled) "h" "l" st d0 d2 d3 d4 d5 sp d1 d6 d7 p st d0 d2 d3 d4 d5 sp d1 d6 d7 p rxdi (not inverted) "h" "l" st d0 d2 d3 d4 d5 sp d1 d6 d7 p st d0 d2 d3 d4 d5 sp d1 d6 d7 p txdi (inverted) "h" "l" rxdi (inverted) "h" "l" st: start bit p: parity bit sp: stop bit m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 223 of 352 rej09b0385-0100 17.1.2.5 cts/rts function ? cts function transmit operation is controlled by using the input signal to the ctsi pin . to use the cts function, select the i/o port in the function select register, set the crd bit in the uic0 register to 0 (cts function enabled), and the crs bit to 0 (cts function selected). with the cts function used, the tran smit operation starts when all the following conditions are met and an ?l? signal is applied to the ctsi pin (i = 0 to 4). -the te bit in the uic1 register is set to 1 (transmit operation enabled) -the ti bit in the uic1 regi ster is 0 (data in the uitb register) when a high-level (?h?) sign al is applied to the ctsi pin during transmitting, the transmit operation is disabled after the transmit operation in progress is completed. ? rts function the mcu can inform the external devi ce that it is ready for a receive operation by usin g the output signal from the rtsi pin. to use the rts function, select the rtsi pin in the function select register. with the rts function used, the rtsi pin outputs an ?l? signal when all the following conditions are met, and outputs an ?h? when th e start bit is detected. -the ri bit in the uic1 register is 0 (no data in the uirb register) -the re bit is set to 1 (receive operation enabled) 17.1.2.6 procedure when the co mmunication error is occurred follow the procedure below when a communi cation error is occurred in uart mode. (1) set the te bit in the uic1 register (i = 0 to 4) to 0 (transmit operation disabled) and the re bit to 0 (receive operation disabled). (2) set bits smd2 to smd0 in the uimr register to 000b (serial interface disabled). (3) set bits smd2 to smd0 in the uimr register to 100b (uart mode, 7-bit data length), 101b (uart mode, 8-bit data length), or 110b (uart mode, 9-bit data length). (4) set the te bit to 1 (transmit operation enabled) and the re bi t to 1 (receive operation enabled). m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 224 of 352 rej09b0385-0100 17.1.3 special mode 1 (i 2 c mode) in i 2 c mode, the simplified i 2 c helps to communicate w ith external devices. table 17.6 lists specifications of i 2 c mode. tables 17.7 and 17.8 list regist er settings. tables 17.9 and 17.10 list individual functions in i 2 c mode. table 17.11 lists pin settings. figure 17.23 shows a block diagram of i 2 c mode. figure 17.24 shows a transfer timing to the uirb register (i = 0 to 4) and interrupt timing. table 17.6 i 2 c mode specifications notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. if an external clock is selected, satisfy the conditions while an ?h? signal is applied to the scli pin. 3. if an overrun error occurs, a read from the uirb register returns undefined values. the ir bit in the siric register remains unchanged as 0 (interrupt not requested). item specification data format ? data length: 8 bits long baud rate ? in master mode when the ckdir bit in the uimr register (i = 0 to 4) is set to 0 (internal clock): fj / (2 (m + 1)) fj = f1, f8, f2n (1) m: setting value of the uibrg register (00h to ffh) ? in slave mode when the ckdir bit is set to 1 (external clock): input from the scli pin transmit start condition to start transmit operation, all of the following must be met (2) : ? set the te bit in the uic1 register to 1 (transmit operation enabled) ? the ti bit in the uic1 register is 0 (data in the uitb register) receive start condition to start receive operation, all of the following must be met (2) : ? set the te bit to 1 (transmit operation enabled) ? the ti bit is 0 (data in the uitb register) ? set the re bit in the uic1 register to 1 (receive operation enabled) interrupt request generation timing ? start condition detection ? stop condition detection ? ack (acknowledge) detection ? nack (not-acknowledge) detection error detection ? overrun error (3) overrun error occurs when the 8th bit of the next data is received before reading the uirb register selectable function ? arbitration lost detect timing update timing of the abt bit in the uirb register (i = 0 to 4) can be selected. refer to 17.1.3.3 arbitration ? sdai digital delay no digital delay or 2 to 8 cycle delay of the uibrg count source can be selected. refer to 17.1.3.5 sda output ? clock phase setting clock delay or no clock delay can be selected. refer to 17.1.3.4 serial clock. m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 225 of 352 rej09b0385-0100 figure 17.23 i 2 c mode block diagram sdhi als ackc 0 1 stspsel 0 1 delay circuit d q t uarti transmit shift register start condition detection stop condition detection sdai select sda output in function control register scli select scl output in function control register ackd noise filter noise filter uarti clk control s q r s q r swc swc2 falling edge of 9th bit transmission control circuit uarti transmit interrupt request nack interrupt request dma 0 to 3 request uarti transmit shift register start/stop condition detection interrupt request s q r reception control circuit uarti receive interrupt request ack interrupt request dma 0 to 3 request d q t 9th clock nack ack logic 0 write signal to pdk_m logic 1 write signal to pdk_m d q t iicm2 = 1 iicm = 1 and iicm2 = 0 iicm = 0 or iicm2 = 1 iicm = 1 and iicm2 = 0 abt bbs i = 0 to 4 iicm, bbs: bits in the uismr register iicm2, swc, als, swc2, sdhi: bits in the uismr2 register stspsel, ackd, ackc: bits in the uismr4 register nch: bit in the uic0 register abt: uirb register pdk_m: bit in the port pk direction register corresponding to t he scli pin note: 1. p7_0 and p7_1 do not have the dotted rectangular portio n of the circuit. stspsel iicm 0 1 0 1 start/stop condition generation block falling edge detection nch nch (note 1) (note 1) m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 226 of 352 rej09b0385-0100 table 17.7 register settings in i 2 c mode (1) i = 0 to 4 register bit setting value master slave uimr smd2 to smd0 set to 010b ckdir set to 0 set to 1 iopol set to 0 uismr iicm set to 1 abc select an arbitration lost detect timing disabled bbs bus busy flag 7 to 3 set to 00000b uismr2 iicm2 see table 17.9 and 17.10 functions in i 2 c mode csc set to 1 to enable clock synchronization set to 0 swc set to 1 to hold an ?l? signal output from scli at the falling edge of the ninth bit of the serial clock als set to 1 to abort an sdai output when detecting the arbitration lost set to 0 stc set to 0 set to 1 to initialize uarti by detecting the start condition swc2 set to 1 to forcibly make a signal output from scl an ?l? sdhi set to 1 to disable sda output su1him set to 0 uismr3 sse set to 0 ckph see table 17.9 and 17.10 functions in i 2 c mode dinc, nodc, err set to 0 dl2 to dl0 set sdai digital delay value uismr4 stareq set to 1 to generate the start condition set to 0 rstareq set to 1 to generate the restart condition stpreq set to 1 to generate the stop condition stspsel set to 1 when using a condition generation function ackd select ack or nack ackc set to 1 to output ack data sclhi set to 1 to enable scl output stop when detecting the stop condition set to 0 swc9 set to 0 set to 1 to hold an ?l? signal output from scli at the falling edge of the ninth bit of the serial clock m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 227 of 352 rej09b0385-0100 table 17.8 register settings in i 2 c mode (2) i = 0 to 4 register bit setting value master slave uic0 clk1, clk0 select the count source of the uibrg register disabled crs disabled because the crd bit is set to 1 txept transmit shift register empty flag crd, nch set to 1 ckpol set to 0 uform set to 1 uic1 te set to 1 to enable transmit operation ti uitb register empty flag re set to 1 to enable receive operation ri receive operation complete flag uilch, uiere set to 0 uibrg 7 to 0 set baud rate disabled ifsr ifsr7, ifsr6 select the uarti interrupt source uitb 7 to 0 set transmit data uirb 7 to 0 receive data can be read 8 ack or nack is received abt arbitration lost detect flag disabled oer overrun error flag m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 228 of 352 rej09b0385-0100 as shown in table 17.9, i 2 c mode is entered when bits smd2 to sm d0 in the uimr register are set to 010b (i 2 c mode) and the iicm bit in the uismr register to 1 (i 2 c mode). because an sdai transmit output passes through a delay circuit, output signal from the sdai pin changes after the scli pin level becomes low (?l?) and the ?l? output stabilizes. table 17.9 functions in i 2 c mode (1) i = 0 to 4 note: 1. use the following procedures to change an interrupt source. (a) disable an interrupt of the corresponding interrupt number. (b) change an interrupt source. (c) set the ir bit of a corresponding interrupt number to 0 (interrupt not requested). (d) set bits ilvl2 to ilvl0 of the corresponding interrupt number. function i 2 c mode (smd2 to smd0 = 010b, iicm = 1) iicm2 = 0 (nack/ack interrupt) iicm2 = 1 (uart transmit/receive interrupt) ckph = 0 (no clock delay) ckph = 1 (clock delay) ckph = 0 (no clock delay) ckph = 1 (clock delay) interrupt source for numbers 39 to 41 (1) (see figure 17.24 ) start condition or stop condition detection (see table 17.12 stspsel bit function) interrupt source for numbers 17, 19, 33, 35, 37 (1) (see figure 17.24 ) no acknowledgement detection (nacki) - at the rising edge of 9th bit of scli uarti transmit operation - at the rising edge of 9th bit of scli uarti transmit operation - at the next falling edge after the 9th bit of scli interrupt source for numbers 18, 20, 34, 36, 38 (1) (see figure 17.24 ) acknowledgement detection (acki) - at the rising edge of 9th bit of scli uarti receive operation - at the falling edge of 9th bit of scli data transfer timing from the uart receive shift register to the uirb register at rising edge of 9th bit of scli falling edge of 9th bit of scli falling edge and rising edge of 9th bit of scli uarti transmit output delay delay functions of p6_3, p6_7, p7_0, p9_2, p9_6 sdai input and output functions of p6_2, p6_6, p7_1, p9_1, p9_7 scli input and output noise filter width 200 ns m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 229 of 352 rej09b0385-0100 table 17.10 functions in i 2 c mode (2) i = 0 to 4 notes: 1. set default value of the sdai output while bits smd2 to smd0 in the uimr register are set to 000b (serial interface disabled). 2. second data transfer to the uirb register (at the rising edge of the ninth bit of scli). 3. first data transfer to the uirb register (at the falling edge of the ninth bit of scli). function i 2 c mode (smd2 to smd0 = 010b, iicm = 1) iicm2 = 0 (nack/ack interrupt) iicm2 = 1 (uart transmit/receive interrupt) ckph = 0 (no clock delay) ckph = 1 (clock delay) ckph = 0 (no clock delay) ckph = 1 (clock delay) reading rxdi, scli pin levels can be read regardless of the corresponding port direction bit default value of txdi, sdai output value set in the port register before entering i 2 c mode (1) scli default and end values hl h l dma source (see figure 17.24 ) acknowledgement detection (acki) uarti receive operation - at the falling edge of 9th bit of scli storing receive data 1st to 8th bit of the receive data are stored into bits 7 to 0 in the uirb register 1st to 7th bits of the receive data are stored into bits 6 to 0 in the uirb register. 8th bit is stored into bit 8 in the uirb register 1st to 8th bits are stored into bits 7 to 0 in the uirb register (2) reading receive data the value in the uirb register is read as it is bits 6 to 0 in the uirb register are read as bits 7 to 1. bit 8 in the uirb register is read as bit 0 (3) m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 230 of 352 rej09b0385-0100 figure 17.24 transfer timing to the uirb register and interrupt timing scli (1) when the iicm2 bit is set to 0 (ack or nack inte rrupt) and the ckph bit is set to 0 (no clock delay) d7 d6 d4 d3 d2 d1 d5 sdai i = 0 to 4 the above applies when the ckdir bit in uimr register = 1 (external clock selected) d0 d8 (ack,nack) ack interrupt (dma request) or nack interrupt transferred to the uirb register d8 d7 d6 d5 d4 d3 d2 d1 1st bit 2nd bit 3rd bit 4th bit 5th bi t 6th bit 7th bit 8th bit 9th bit b15 b9 b8 b7 b0 scli (2) when the iicm2 bit is set to 0 and th e ckph bit is set to 1 (clock delay) d7 d6 d4 d3 d2 d1 d5 sdai d0 d8 (ack, nack) scli (3)when the iicm2 bit is set to 1 (uart transmit or receive interrupt) and the ckph bit is set to 0 d7 d6 d4 d3 d2 d1 d5 sdai d0 d8 (ack,nack) ack interrupt (dma request) or nack interrupt transferred to the uirb register d8 d7 d6 d5 d4 d3 d2 d1 b15 b9 b8 b7 b0 receive interrupt (dma request) transmit interrupt d0 ? d7 d6 d5 d4 d3 d2 b15 b9 b8 b7 b0 scli (4) when the iicm2 bit is set to 1 and the ckph bit is set to 1 d7 d6 d4 d3 d2 d1 d5 sdai d0 d8 (ack, nack) contents of the uirb register contents of the uirb register transferred to the uirb register contents of the uirb register receive interrupt (dma request) transmit interrupt d0 ? d7 d6 d5 d4 d3 d2 b15 b9 b8 b7 b0 transferred to the uirb register (first time) contents of the uirb register transferred to the uirb register (second time) d8 d7 d6 d5 d4 d3 d2 d1 b15 b9 b8 b7 b0 contents of the uirb register d0 d0 d1 d0 d1 1st bit 2nd bit 3rd bit 4th bit 5th bi t 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bi t 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bi t 6th bit 7th bit 8th bit 9th bit m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 231 of 352 rej09b0385-0100 table 17.11 pin settings in i 2 c mode notes: 1. set registers ps0, ps1, and ps3 after setting other registers. 2. set the pd9 or ps3 register immediately after the prc2 bit in the prcr register is set to 1 (write enable). do not generate an interrupt or a dma or dmacii transfer between these two instructions. 3. p7_0 and p7_1 are n-channel open drain output ports. port function bit setting pd6, pd7, pd9 registers (2) psc register psl0, psl1, psl3 registers ps0, ps1, ps3 registers (1)(2) p6_2 scl0 output ?? psl0_2 = 0 ps0_2 = 1 scl0 input pd6_2 = 0 ?? ps0_2 = 0 p6_3 sda0 output ?? psl0_3 = 0 ps0_3 = 1 sda0 input pd6_3 = 0 ?? ps0_3 = 0 p6_6 scl1 output ?? psl0_6 = 0 ps0_6 = 1 scl1 input pd6_6 = 0 ?? ps0_6 = 0 p6_7 sda1 output ?? psl0_7 = 0 ps0_7 = 1 sda1 input pd6_7 = 0 ?? ps0_7 = 0 p7_0 (3) sda2 output ? psc_0 = 0 psl1_0 = 0 ps1_0 = 1 sda2 input pd7_0 = 0 ?? ps1_0 = 0 p7_1 (3) scl2 output ? psc_1 = 0 psl1_1 = 0 ps1_1 = 1 scl2 input pd7_1 = 0 ?? ps1_1 = 0 p9_1 scl3 output ?? psl3_1 = 0 ps3_1 = 1 scl3 input pd9_1 = 0 ?? ps3_1 = 0 p9_2 sda3 output ?? psl3_2 = 0 ps3_2 = 1 sda3 input pd9_2 = 0 ?? ps3_2 = 0 p9_6 sda4 output ??? ps3_6 = 1 sda4 input pd9_6 = 0 ? ps3_6 = 0 p9_7 scl4 output ?? psl3_7 = 0 ps3_7 = 1 scl4 input pd9_7 = 0 ?? ps3_7 = 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 232 of 352 rej09b0385-0100 17.1.3.1 detecting start c ondition and stop condition the mcu detects the start condition and stop condition. the start condition detection interrupt request is generated when the sdai (i = 0 to 4) pin level change s from high (?h?) to low (?l?) while the scli pin level is held ?h?. the stop condition detection interrupt request is generated when the sdai pin level changes from ?l? to ?h? while the scli pin level is held ?h?. the start condition detection interrupt shares the interrupt control register and interrupt vector with the stop condition detection interrupt. the bbs bit in the uismr register determines which interrupt is requested. figure 17.25 start condition or stop condition detection 17.1.3.2 start condition or stop condition output the start condition is generated when the stareq bit in th e uismr4 register (i = 0 to 4) is set to 1 (start). the restart condition is generated when the rstareq bit in the uismr4 register is set to 1 (start). the stop condition is generated when the stpreq bit in the uismr4 is set to 1 (start). the following is the procedure to output the star t condition, restart condition, or stop condition. (1) set the stareq bit, rstareq bit, or stpreq bit to 1 (start). (2) set the stspsel bit in the uismr4 register to 1 (start/stop condition generation circuit selected). table 17.12 and figure 17.26 show functions of the stspsel bit. table 17.12 stspsel bit function function stspsel = 0 stspsel = 1 output from pins scli and sdai output the serial clock and data. output of the start condition or stop condition is controlled by software utilizing port functions. (the start condition and stop condition are not automatically generated by hardware) output of the start condition or stop condition is controlled by the status of bits stareq, rstareq, and stpreq. timing to generate start condition and stop condition interrupt requests when start condition and stop condition are detected when start condition and stop condition generation are completed i=0 to 4 note: 1. these are cycles of t he main clock oscillation frequency f(xin) . sdai (stop condition) 6 cycles < setup time (1) 6 cycles < hold time (1) setup time hold time scli sdai (start condition) m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 233 of 352 rej09b0385-0100 figure 17.26 stspsel bit function scli sdai i = 0 to 4 (1) in slave mode, the ckdir bit is set to 1 (external clock) and the stsp sel bit is set to 0 (no start condition and stop condition output) (2) in master mode, the ckdir bit is set to 0 (internal clock) and the stspsel bit is set to 1 (start condition and stop condition output) start condition detection interrupt scli sdai start condition detection interrupt stop condition detection interrupt 01 0 0 1 setting value of stspsel bit the stareq bit is set to 1 (start) the stareq bit is set to 1 (start) stop condition detection interrupt 1 0 ir bit in the bcniic register set to 0 by an interrupt req uest acknowledgement or by program 1 0 ir bit in the bcniic register set to 0 by an interrupt request acknowledgement or by program m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 234 of 352 rej09b0385-0100 17.1.3.3 arbitration the abc bit in the uismr register (i = 0 to 4) determines an update timing of the abt bit in the uirb register. at the rising edge of the clock input to the scli pin, the mcu determines whether a transmit data matches data input to the sdai pin. when the abc bit is set to 0 (update per bit), the abt bit becomes 1 (detected - arbitration is lost) as soon as a data discrepancy is detected. the abt bit remains 0 (not detected - arbitration is won) if not detected. when the abc bit is set to 1 (update per byte), the abt bit becomes 1 at the falling edge of th e ninth cycle of the serial clock if discrepancy is ever detected. when the abt bit is updated per byte, set the abt bit to 0 after an ack detection in the first byte data is completed. then the next byte data transfer can be started. when the als bit in the uismr2 register is set to 1 (sdai output stopped) and the abt bit becomes 1 (detected - arbitration is lost), the sdai pin is placed in a high-impedance state simultaneously. 17.1.3.4 serial clock the serial clock is used to transmit and receive data as is shown in figure 17.24. by setting the csc bit in the uismr2 register to 1 (clock synchronized), an internally generated clock (internal scli) is synchronized with the external clock applied to the scli pin. if the csc bit is set to 1, the internal scli becomes low (?l?) when the internal scli is held high (?h?) and the external clock applied to the scli pin is at the falling edge. the contents of the uibrg register are reloaded and a counting for ?l? period is started. when the external clock applie d to scli pin is held ?l? and then the internal scli changes ?l? to ?h?, the uibrg counter stops. the counting is resumed when the clock applied to scli pin becomes ?h?. the uarti serial clock is equivalent to logical and operati on of the internal scli and the clock signal applied to the scli pin. the serial clock is synchronized betw een a half cycle before the falling edge of the first bit and the rising edge of the ninth bit of the internal scli. select the internal clock as the serial clock while the csc bit is set to 1. the swc bit in the uismr2 register de termines whether an output signal fr om the scli pin is held ?l? at the falling edge of the ninth cycl e of the serial clock or not. when the sclhi bit in the uismr4 register is set to 1 (scli output stopped), a scli output stops as soon as the stop condition is detected (the scli pin is in a high-impedance state). when the swc2 bit in the uismr2 register is set to 1 (scli pin is held ?l?), the scli pin forcibly outputs an ?l? even in the middle of transmitting and receiving. the fixed ?l? output from the scli pin is cancelled by setting the swc2 bit to 0 (serial clock), and then the serial clock inputs to or outputs from the scli pin. when the ckph bit in the uismr3 regi ster is set to 1 (clock delay) and the swc9 bit in the uismr4 register is set to 1 (scli pin is held ?l? after receiving 9th bit) , an output signal from the scli pin is held ?l? at the next falling edge to the ninth bit of the clock. the fixed ?l? output from the scli pin is cancelled by setting the swc9 bit to 0 (no wait state/release wait state). 17.1.3.5 sda output values set in bits 7 to 0 (d7 to d0) in the uitb register are output in descending order from d7. the ninth bit (d8) is ack or nack. set the default value of sdai transmit output, while the iicm bit in the uismr register is set to 1 (i 2 c mode) and bits smd2 to smd0 in the uimr regist er are set to 000b (serial interface disabled). bits dl2 to dl0 in the uismr3 register determine no delay or delay of 2 to 8 uibrg register count source cycles are added to an sdai output. when the sdhi bit in the uismr2 register is set to 1 (sda output stopped), the sdai pin is forcibly placed in a high-impedance state. do not write to the sdhi bit at the rising edge of the uarti serial clock. the abt bit in the uirb register may become 1 (detected). m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 235 of 352 rej09b0385-0100 17.1.3.6 sda input when the iicm2 bit in the uismr2 register (i = 0 to 4) is set to 0, the first eight bits of received data are stored into bits 7 to 0 (d7 to d0) in the uirb register. the ninth bit (d8) is ack or nack. when the iicm2 bit is set to 1, the firs t seven bits (d7 to d1) of received data are stored into bits 6 to 0 in the uirb register. the eighth bit (d0) is stored into bit 8 in the uirb register. if the iicm2 bit is set to 1 and the ckph bit in the uism r3 register is set to 1 (clock delay), the same data as that of when setting the iicm2 bit to 0 can be returned, by reading the uirb register after the rising edge of the ninth bit of the serial clock. 17.1.3.7 ack, nack when the stspsel bit in the uismr4 register is set to 0 (start/stop condition not output) and the ackc bit in the uismr4 register is set to 1 (ack data output), the sdai pin outputs the setting value, ack or nack, of the ackd bit in the uismr4 register. if the iicm2 bit is set to 0, the nack interrupt request is generated when the sdai pin is held high (?h?) at the rising edge of the ninth bit of the serial clock. the ack interrupt request is generated when the sdai pin is held low (?l?) at the rising edge of the ninth bit of the serial clock. when ack is selected to generate a dma request sour ce, the dma transfer is ac tivated by an ack detection. 17.1.3.8 transmit and receive operation initialization the following occurs when the stc bit in the uismr2 re gister is set to 1 (uarti initialized) and the start condition is detected: ? the uarti transmit shift register is initialized and the contents of the uitb regist er are transferred to the uarti transmit shift register. then, the transmit operatio n is started at the next serial clock input to the scli pin. uarti output value remains the same as when the start condition was detected until the first bit data is output. ? the uarti receive shift register is initialized and the receive operation is started at the next serial clock input to the scli pin. ? the swc bit in the uismr2 register becomes 1 (scli pin is held ?l? after receiving 8th bit). an output from the scli pin becomes ?l? at the falling edge of the ninth bit of the serial clock. when uarti transmit/receive operation is started with se tting the stc bit to 1, the ti bit in the uic1 register remains unchanged. also, select the external clock as th e serial clock to start uarti transmit/receive operation with setting the stc bit to 1. m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 236 of 352 rej09b0385-0100 17.1.4 special mode 2 full-duplex clock synchronous serial communications are al lowed in this mode. ss function is used for transmit and receive control. the input signal to the ssi pin (i = 0 to 4) determines whether the transmit and receive operation is enabled or disabled. when it is disabled, the output pin is placed in a high -impedance state. table 17.13 lists specifications of special mode 2. table 17.14 list pin settings. figure 17.27 shows register settings. table 17.13 special mode 2 specifications notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. if an external clock is selected, ensure that an ?h? signal is applied to the clki pin when the ckpol bit in the uic0 register is set to 0, and that an ?l? signal is applied when the ckpol bit is set to 1. 3. if an overrun error occurs, a read from the uirb register returns undefined values. the ir bit in the siric register remains unchanged as 0 (interrupt not requested). item specification data format data length: 8 bits long baud rate ? the ckdir bit in the uimr register (i = 0 to 4) is set to 0 (internal clock): fj / (2 (m + 1)) fj = f1, f8, f2n (1) m: setting value of the uibrg register (00h to ffh) ? the ckdir bit to 1 (external clock): input from the clki pin transmit/receive control ss function output pin is placed in a high-impedance state to avoid data conflict between a master and other masters, or a slave and other slaves. transmit and receive start condition internal clock is selected (master mode): ? set the te bit in the uic1 register to 1 (transmit operation enabled) ? the ti bit in the uic1 register is 0 (data in the uitb register) ? set the re bit in the uic1 register to 1 (receive operation enabled) ? ?h? signal is applied to the ssi pin when the ss function is used external clock is selected (slave mode) (2) : ? set the te bit to 1 ? the ti bit is 0 ? set the re bit to 1 ? ?l? signal is applied to the ssi pin if transmit-only operation is performed, the re bit setting is not required in both cases. interrupt request generation timing transmit interrupt (the uiirs bit in the uic1 register selects one of the following): ? the uiirs bit is set to 0 (no data in the uitb register): when data is transferred from the uitb r egister to the uarti transmit shift register (transmit operation started) ? the uiirs bit is set to 1 (transmit operation completed): when data transmit operation from the uarti transmit shift register is completed receive interrupt: ? when data is transferred from the uarti re ceive shift register to the uirb register (receive operation completed) error detection ? overrun error (3) overrun error occurs when the 7th bit of the next data is received before reading the uirb register ? mode error mode error occurs when an ?l? signal is applied to the ssi pin in master mode selectable function ? clk polarity transmit data output timing and receive data input timing can be selected ? lsb first or msb first data is transmitted or received from either bit 0 or bit 7 ? serial data logic inverse transmit and receive data are logically inverted ? txd and rxd i/o polarity inverse the level output from the txd pin and the level applied to the rxd pin are inverted. ? clock phase one of four combinations of serial clock polarity and phase can be selected m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 237 of 352 rej09b0385-0100 table 17.14 pin settin gs in special mode 2 notes: 1. set registers ps0, ps1, and ps3 after setting other registers. 2. set the pd9 or ps3 register immediately after the prc2 bit in the prcr register is set to 1 (write enable). do not generate an interrupt or a dma or dmacii transfer between these two instructions. 3. p7_0 and p7_1 are n-channel open drain output ports. port function bit setting pd6, pd7, pd9 registers (2) psc register psl0, psl1, psl3 registers ps0, ps1, ps3 registers (1)(2) p6_0 ss0 input pd6_0 = 0 ?? ps0_0 = 0 p6_1 clk0 output (master) ?? psl0_1 = 0 ps0_1 = 1 clk0 input (slave) pd6_1 = 0 ?? ps0_1 = 0 p6_2 rxd0 input (master) pd6_2 = 0 ?? ps0_2 = 0 stxd0 output (slave) ?? psl0_2 = 1 ps0_2 = 1 p6_3 txd0 output (master) ?? psl0_3 = 0 ps0_3 = 1 srxd0 input (slave) pd6_3 = 0 ?? ps0_3 = 0 p6_4 ss1 input pd6_4 = 0 ?? ps0_4 = 0 p6_5 clk1 output (master) ?? psl0_5 = 0 ps0_5 = 1 clk1 input (slave) pd6_5 = 0 ?? ps0_5 = 0 p6_6 rxd1 input (master) pd6_6 = 0 ?? ps0_6 = 0 stxd1 output (slave) ?? psl0_6 = 1 ps0_6 = 1 p6_7 txd1 output (master) ?? psl0_7 = 0 ps0_7 = 1 srxd1 input (slave) pd6_7 = 0 ?? ps0_7 = 0 p7_0 (3) txd2 output (master) ? psc_0 = 0 psl1_0 = 0 ps1_0 = 1 srxd2 input (slave) pd7_0 = 0 ?? ps1_0 = 0 p7_1 (3) rxd2 input (master) pd7_1 = 0 ?? ps1_1 = 0 stxd2 output (slave) ?? psl1_1 = 1 ps1_1 = 1 p7_2 clk2 output (master) ? psc_2 = 0 psl1_2 = 0 ps1_2 = 1 clk2 input (slave) pd7_2 = 0 ?? ps1_2 = 0 p7_3 ss2 input pd7_3 = 0 ?? ps1_3 = 0 p9_0 clk3 output (master) ?? psl3_0 = 0 ps3_0 = 1 clk3 input (slave) pd9_0 = 0 ?? ps3_0 = 0 p9_1 rxd3 input (master) pd9_1 = 0 ?? ps3_1 = 0 stxd3 output (slave) ?? psl3_1 = 1 ps3_1 = 1 p9_2 txd3 output (master) ?? psl3_2 = 0 ps3_2 = 1 srxd3 input (slave) pd9_2 = 0 ?? ps3_2 = 0 p9_3 ss3 input pd9_3 = 0 ? psl3_3 = 0 ps3_3 = 0 p9_4 ss4 input pd9_4 = 0 ? psl3_4 = 0 ps3_4 = 0 p9_5 clk4 output (master) ??? ps3_5 = 1 clk4 input (slave) pd9_5 = 0 ? psl3_5 = 0 ps3_5 = 0 p9_6 txd4 output (master) ??? ps3_6 = 1 srxd4 input (slave) pd9_6 = 0 ? psl3_6 = 0 ps3_6 = 0 p9_7 rxd4 input (master) pd9_7 = 0 ?? ps3_7 = 0 stxd4 output (slave) ?? psl3_7 = 1 ps3_7 = 1 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 238 of 352 rej09b0385-0100 figure 17.27 register settings in special mode 2 end initial setting i = 0 to 4 notes: 1. set to 0 in master m ode, and set to 1 in slave mode. 2. the clock phase is determi ned by the combination of the ckph and ckpol bits in the uismr3 register. 3. bits cnt3 to cnt0 select no division (n = 0) or divide- by-2n (n = 1 to 15). uimr register: bits smd2 to smd0 = 001b ckdir bit iopol bit = 0 clock synchronous mode clock select bit (1) uismr register = 00h uismr2 register = 00h uismr4 register = 00h uic0 register: bits clk1 to clk0 crd bit = 1 nch bit ckpol bit uform bit uibrg count source select bits cts function disabled data output select bit clk polarity select bit (2) bit order select bit m = 00h to ffh baud rate = uic1 register: te bit = 0 re bit = 0 uiirs bit uirrm bit = 0 uilch bit = 0 bit 7 = 0 transmit operation disabled receive operation disabled uarti transmit interrupt souce select bit pin setting in the function select registers fj 2(m + 1) fj: f1, f8, f2n (3) < when an internal clock is used > transmit/receive operation starts by writing data to uitb regis ter. read the uirb register when the receive operation is completed. uismr3 register: sse bit = 1 ckph bit dinc bit nodc bit = 0 bits dl2 to dl0 = 000b ss function enabled clock phase set bit (2) serial input pin set bit (1) start initial setting transmit operation enabled receive operation enabled uic1 register: te bit = 1 re bit = 1 transmit interrupt priority level select bit interrupt not requested sitic register: bits ilvl2 to ilvl0 ir bit = 0 receive interrupt prior ity level select bit interrupt not requested siric register: bits ilvl2 to ilvl0 ir bit = 0 interrupt enabled i flag = 1 interrupt disabled i flag = 0 uibrg register = m m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 239 of 352 rej09b0385-0100 17.1.4.1 master mode master mode is entered when the dinc bit in the uismr3 register (i = 0 to 4) is set to 1. the following pins are used in master mode. ? txdi: transmit data output ? rxdi: receive data input ? clki: serial clock output to use the ss function, set the sse bit in the uismr3 register to 1. a transmit and receive operation is performed while an ?h? is applied to the ssi pin. if an ?l? is applied to the ssi pin, the err bit in the uismr3 register becomes 1 (mode er ror occurred) and pins clki and txdi are placed in high-impedance states. set the uiirs bit in the uic1 register to 1 (tra nsmit completion as interrupt source) to verify whether a mode error has occurred or not by checking the eer bit in the transmission complete interrupt routine. to resume serial communication after a mode error occurs, set the err bit to 0 (no mode error) while an ?h? signal is applied to the ssi pin. pins txdi and clki become in output mode. 17.1.4.2 slave mode slave mode is entered when the dinc bit in the uismr3 register is set to 0. the following pins are used in slave mode. ? stxdi: transmit data output ? srxdi: receive data input ? clki: serial clock input to use the ss function, set the sse bit in the uismr3 regi ster to 1. when an ?l? signal is applied to the ssi input pin, the serial clock input is enabled, and a tr ansmit and receive operation becomes available. when an ?h? signal is applied to the ssi pin, the serial clock input to the cl ki pin is ignored and the stxdi pin is placed in a high-impedance state. figure 17.28 serial bus communication control with ssi pin mcu p1_3 p1_2 p9_3(ss3) p9_0(clk3) p9_1(rxd3) p9_2(txd3) mcu mcu (slave) (master) p9_3(ss3) p9_0(clk3) p9_1(stxd3) p9_2(srxd3) p9_3(ss3) p9_0(clk3) p9_1(stxd3) p9_2(srxd3) (slave) m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 240 of 352 rej09b0385-0100 17.1.4.3 clock phase setting function the clock polarity and clock phase are selected from f our combinations of the ckph and ckpol bits in the uismr3 register (i = 0 to 4). the master must have the same serial clock polarity and phase as the slaves involved in the communication. figure 17.29 shows a transmit and receive operation timing. figure 17.29 transmit and receive operation timing in special mode 2 d0 d1 clki i/o (ckpol = 0) clki i/o (ckpol = 1) h l d2 d3 d4 d5 d6 d7 h l h l h l d0 undefined d1 h l i=0 to 4 ckph, dinc: bits in the uismr3 register ckpol: bit in the uic0 register note: 1. p7_0 and p7_1 are n-channel open drain output ports. t hey must be pulled up externally to output data. d2 d3 d4 d5 d6 d7 h l hi-z clki i/o (ckpol = 0) clki i/o (ckpol = 1) h l h l hi-z d1 d0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 (1) when the ckph = 0 (no clock delay) (2) when the ckph = 1 (clock delay) in master mode (internal clock) (dinc = 0) in slave mode (external clock) (dinc = 1) ssi input pin txdi output ssi input pin stxdi output (1) receive data input timing receive data input timing h l h l in slave mode (external clock) (dinc = 1) ssi input pin stxdi output (1) receive data input timing h l h l in master mode (internal clock) (dinc = 0) ssi input pin txdi output receive data input timing hi-z hi-z m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 241 of 352 rej09b0385-0100 17.1.5 special mode 3 (gci mode) full-duplex clock synchronous serial communications are a llowed in this mode. when a trigger is input to the ctsi (i = 0 to 4) pin, the internal clock which is synchronized with the continuous external clock is generated, and a transmit and receive operation is started. table 17.15 lists specifications of gci mode. table 17.16 list pin settings. figure 17.30 shows register settings. table 17.15 gci mode specifications note: 1. if an overrun error occurs, a read from the uirb register returns undefined values. the ir bit in the siric register remains unchanged as 0 (interrupt not requested). item specification data format data length: 8 bits long serial clock select the external clock set the ckdir bit in the uimr register (i = 0 to 4) to 1 (external clock). when a trigger is input, the external clock or the clock divided by 2 becomes the serial clock. transmit and receive start condition a transmit and receive operation starts when a trigger is input to the ctsi pin after all the following are met: ? set the te bit in the uic1 register to 1 (transmit operation enabled) ? the ti bit in the uic1 register is 1 (data in the uitb register) ? set the re bit in the uic1 register to 1 (receive operation enabled) ? set the sclkstpb bit in the uic1 register is set to 0 (clock-divided synchronization stopped) the sclkstpb bit becomes 1 (clock-divided synchronization started) when a trigger is input to the ctsi pin transmit and receive stop condition the sclkstpb bit in the uic1 register is set to 0 interrupt request generation timing transmit interrupt (the uiirs bit in the uic1 register selects one of the following): ? the uiirs bit is set to 0 (no data in the uitb register): when data is transferred from the uitb register to the uarti transmit shift register (transmit operation started) ? the uiirs bit is set to 1 (transmit operation completed): when data transmit operation from the uarti transmit shift register is completed receive interrupt: ? when data is transferred from the uarti receive shift register to the uirb register (receive operation completed) error detection overrun error (1) overrun error occurs when the 7th bit of the next data is received before reading the uirb register m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 242 of 352 rej09b0385-0100 table 17.16 pin settings in gci mode notes: 1. set registers ps0, ps1, and ps3 after setting other registers. 2. set the pd9 or ps3 register immediately after the prc2 bit in the prcr register is set to 1 (write enable). do not generate an interrupt or a dma or dmacii transfer between these two instructions. 3. cts input is used as a trigger signal input. 4. p7_0 is an n-channel open drain output port. port function bit setting pd6, pd7, pd9 registers (2) psc register psl0, psl1, psl3 registers ps0, ps1, ps3 registers (1)(2) p6_0 cts0 input (3) pd6_0 = 0 ?? ps0_0 = 0 p6_1 clk0 input pd6_1 = 0 ?? ps0_1 = 0 p6_2 rxd0 input pd6_2 = 0 ?? ps0_2 = 0 p6_3 txd0 output ?? psl0_3 = 0 ps0_3 = 1 p6_4 cts1 input (3) pd6_4 = 0 ?? ps0_4 = 0 p6_5 clk1 input pd6_5 = 0 ?? ps0_5 = 0 p6_6 rxd1 input pd6_6 = 0 ?? ps0_6 = 0 p6_7 txd1 output ?? psl0_7 = 0 ps0_7 = 1 p7_0 (4) txd2 output ? psc_0 = 0 psl1_0 = 0 ps1_0 = 1 p7_1 rxd2 input pd7_1 = 0 ?? ps1_1 = 0 p7_2 clk2 input pd7_2 = 0 ?? ps1_2 = 0 p7_3 cts2 input (3) pd7_3 = 0 ?? ps1_3 = 0 p9_0 clk3 input pd9_0 = 0 ?? ps3_0 = 0 p9_1 rxd3 input pd9_1 = 0 ?? ps3_1 = 0 p9_2 txd3 output ?? psl3_2 = 0 ps3_2 = 1 p9_3 cts3 input (3) pd9_3 = 0 ? psl3_3 = 0 ps3_3 = 0 p9_4 cts4 input (3) pd9_4 = 0 ? psl3_4 = 0 ps3_4 = 0 p9_5 clk4 input pd9_5 = 0 ? psl3_5 = 0 ps3_5 = 0 p9_6 txd4 output ??? ps3_6 = 1 p9_7 rxd4 input pd9_7 = 0 ?? ps3_7 = 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 243 of 352 rej09b0385-0100 figure 17.30 register settings in gci mode end initial setting i = 0 to 4 note: 1. the external clock synchronization function is determin ed by the combination of the sclkdiv bit in the uismr register and the su1him bit in the uismr2 register. refer to the table " clock-divided synchronous function select " for details. uimr register: bits smd2 to smd0 = 001b ckdir bit = 1 iopol bit = 0 uismr register: bits 6 to 0 = 0000000b sclkdiv bit uic0 register: bits clk1 and clk0 = 00b crd bit = 1 nch bit ckpol bit = 0 uform bit = 0 uic1 register: te bit = 0 re bit = 0 uiirs bit uirrm bit = 0 uilch bit = 0 sclkstpb bit = 0 pin setting in the function select registers transmit/receive operation star ts when a trigger is input to th e ctsi pin after writing data to the uitb register. read the uirb register when a receive operation is completed. uismr3 register = 00h uismr4 register = 00h uismr2 register: bits 6 to 0 = 0000000b su1him bit uibrg register = 00h start initial setting transmit operation enabled receive operation enabled uic1 register: te bit = 1 re bit = 1 transmit interrupt priority level select bits interrupt not requested sitic register: bits ilvl2 to ilvl0 ir bit = 0 receive interrupt prior ity level select bits interrupt not requested siric register: bits ilvl2 to ilvl0 ir bit = 0 clock synchronous mode select external clock cts function disabled data output select bit transmit operation disabled receive operation disabled uarti transmit interrupt source select bit clock-divided synchronization stopped clock division synchronous bit (1) external clock synchronous enable bit (1) interrupt enabled i flag = 1 interrupt disabled i flag = 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 244 of 352 rej09b0385-0100 set the su1him bit in the uismr2 register (i = 0 to 4) and the sclkdiv bit in the uismr register to values shown in table 17.17, and apply a trigger signal to the ctsi pin. then, the sclkstpb bit becomes 1 and a transmit and receive operation starts. either the same cl ock cycle as the external clock or the external clock cycle divided by two can be se lected for the serial clock. when the sclkstpb bit in the uic1 register is set to 0, a transmissi on and reception in progress stops immediately. figure 17.31 shows an example of the clock-divided synchronous function. table 17.17 clock-d ivided synchronous function select figure 17.31 clock-divided synchronous function sclkdiv bit in the uismr register su1him bit in the uismr2 register clock-divided synchronous function 0 0 not synchronized 0 1 same clock cycle as the external clock 1 0 or 1 external clock cycle divided by 2 external clock from the clki pin serial clock serial clock txdi trigger signal input to the ctsi pin i = 0 to 4 a 13456 2 78 13456 2 78 a: when the sclkdiv bit in the uismr register is set to 0, and the su1him bit in the uismr2 register is set to 1 b: when the sclkdiv bit is set to 1, and su1him bit is set to either 0 or 1. txdi the clock is stopped by the sclkstpb bit in the uic1 register 1 3456 2 78 b more than 1 clock cycle is required m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 245 of 352 rej09b0385-0100 17.1.6 special mode 4 (sim mode) in sim mode, the mcu can communicate with sim interface devices using ua rt mode. both direct and inverse formats are available. the tx di pin (i = 0 to 4) outputs a low-level (?l?) signal when a parity error is detected. table 17.18 lists specifications of sim mode. table 17.19 list pin settings. figure 17.32 lists register settings. figure 17.33 shows an example of sim interface operation. figure 17.34 shows an example of sim interface connection. table 17.18 sim mode specifications notes: 1. bits cnt3 to cnt0 in the tcspr register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. if an overrun error occurs, a read from the uirb register returns undefined values. the ir bit in the siric register remains unchanged as 0 (interrupt not requested). item specification data format ? data length 8-bit uart mode ? one stop bit ? direct format: parity: even data logic: direct (not inverted) bit order: lsb first ? inverse format: parity: odd data logic: inverse (inverted) bit order: msb first baud rate set the ckdir bit in the uimr register is 0 (internal clock): fj / (16 (m + 1)) fj = f1, f8, f2n (1) m: setting value of the uibrg register (00h to ffh) transmit/receive control cts/rts function disabled transmit start condition to start transmit operation, all of the following must be met: ? set the te bit in the uic1 register to 1 (transmit operation enabled) ? the ti bit in the uic1 register is 0 (data in the uitb register) receive start condition to start receive operation, all of the following must be met: ? set the re bit in the uic1 register to 1 (receive operation enabled) ? the start bit is detected interrupt request generation timing transmit interrupt: ? set the uiirs bit to 1 (transmit operation completed) when the stop bit is output from the uarti transmit shift register receive interrupt: ? when data is transferred from the uarti receive shift register to the uirb register (receive operation completed) error detection ? overrun error (2) overrun error occurs when the preceding bit of the stop bit of the next data is received before reading the uirb register ? framing error framing error occurs when the number of the stop bits set using the stps bit in the uimr register is not detected ?parity error parity error occurs when parity is enabled and the received data does not have the correct even or odd parity set with the pry bit in the uimr register. ? error sum flag error sum flag is set to 1 when an overrun, framing, or parity error occurs m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 246 of 352 rej09b0385-0100 table 17.19 pin settings in sim mode notes: 1. set registers ps0, ps1, and ps3 after setting other registers. 2. set the pd9 or ps3 register immediately after the prc2 bit in the prcr register is set to 1 (write enable). do not generate an interrupt or a dma or dmacii transfer between these two instructions. 3. p7_0 is an n-channel open drain output port. port function bit setting pd6, pd7, pd9 registers (2) psc register psl0, psl1, psl3 registers ps0, ps1, ps3 registers (1)(2) p6_2 rxd0 input pd6_2 = 0 ? ps0_2 = 0 p6_3 txd0 output ? psl0_3 = 0 ps0_3 = 1 p6_6 rxd1 input pd6_6 = 0 ? ps0_6 = 0 p6_7 txd1 output ? psl0_7 = 0 ps0_7 = 1 p7_0 (3) txd2 output ? psc_0 = 0 psl1_0 = 0 ps1_0 = 1 p7_1 rxd2 input pd7_1 = 0 ?? ps1_1 = 0 p9_1 rxd3 input pd9_1 = 0 ?? ps3_1 = 0 p9_2 txd3 output ?? psl3_2 = 0 ps3_2 = 1 p9_6 txd4 output ??? ps3_6 = 1 p9_7 rxd4 input pd9_7 = 0 ?? ps3_7 = 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 247 of 352 rej09b0385-0100 figure 17.32 register settings in sim mode i = 0 to 4 notes: 1. set to 1 in the direct fo rmat, and set to 0 in the inve rse format. 2. set to 0 in the direct fo rmat, and set to 1 in the inve rse format. 3. bits cnt3 to cnt0 in the tcspr register select no divis ion (n = 0) or divide-by-2n (n = 1 to 15). 4. determine whether an "l" is output from the txdi pin by reading the port that shares a pin with the rxdi pin in the re ception complete interrupt routine. w hen an "l" is output, wait for on e clock cycle to read the uirb register. uimr register: bits smd2 to smd0 = 101b ckdir bit = 0 stps bit = 0 pry bit prye bit = 1 iopol bit = 0 uart mode: 8-bit data length select internal clock select 1 stop bit parity select bit (1) parity enabled uic0 register: bits clk1 and clk0 crd bit = 1 nch bit = 1 ckpol bit = 0 uform bit uibrg register count source select bits cts function disabled n-channel open drain output bit order select bit (2) uic1 register: te bit = 0 re bit = 0 uiirs bit = 1 uirrm bit = 0 uilch bit uiere bit = 1 transmit operation disabled receive operation disabled transmit completion as transmit interrupt source data logic select bit (2) error signal output enabled pin setting in the function select registers uismr register = 00h uismr2 register = 00h uismr3 register = 00h uismr4 register = 00h m = 00h to ffh baud rate = fj 16(m + 1) fj = f1, f8, f2n (3) uibrg register = m end initial setting start initial setting transmit operation starts by writing data to the uitb register receive operation starts when the start bit is detected. read the uirb register when the receive operation is completed. transmit operation enabled receive operation enabled uic1 register: te bit = 1 re bit = 1 transmit interrupt priority level select bits interrupt not requested sitic register: bits ilvl2 to ilvl0 ir bit = 0 receive interrupt prior ity level select bits interrupt not requested siric register: bits ilvl2 to ilvl0 ir bit = 0 interrupt enabled i flag = 1 interrupt disabled i flag = 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 248 of 352 rej09b0385-0100 figure 17.33 sim interface operation data is transfer from uitb register to uarti transmit shift register "l" level is sent back from the sim card since parity error has occurred data is set in uitb register sp sp stop bit parity bit start bit d7 te bit in the uic1 register the above applies under the following conditions: - uimr register: prye bit = 1 (parity enabled), stps bit = 0 (1 stop bit) - uic1 register: uiirs bit = 1 (transmit interrupt is gene rated at the transmit completion) tc 1 0 internal transmit clock ti bit in the uic1 register txdi output d0 txept bit in the uic0 register ir bit in the sitic register d1 d2 d3 d4 d5 d6 st p d7 d0 d1 d2 d3 d4 d5 d6 st p (2) receive operation re bit in the uic1 register the above applies under the following conditions: - uimr register: prye bit = 1 (parity enabled), stps bit = 0 (1 stop bit) transmit waveform sent by transmitting device ri bit in the uic1 register ir bit in the siric register set to 0 by an interrupt request a cknowledgement or by program 16( m+ 1) fj tc = i = 0 to 4 internal receive clock h l fj: f1, f8, f2n (4) parity error signal sent back from receiving device sp d7 signal line level (2) d0 d1 d2 d3 d4 d5 d6 st p d7 d0 d1 d2 d3 d4 d5 d6 st txdi ouput h l (1) transmit operation signal line level (3) (note 1) detect the level in interrupt routine sp sp stop bit parity bit start bit d7 d0 d1 d2 d3 d4 d5 d6 st p d7 d0 d1 d2 d3 d4 d5 d6 st p tc sp d7 d0 d1 d2 d3 d4 d5 d6 st p d7 d0 d1 d2 d3 d4 d5 d6 st p sp p sp read from the uirb register "l" level is sent back from the sim card since parity error has occurred notes: 1. transmit operation is started when uibrg overflows after data is set in the uitb register in the indicated timing. 2. because pins txdi and rxdi are connected, a composite waveform, consisting of transmit waveform from the txdi pin and p arity error signal from the receiving device, is generated. 3. because pins txdi and rxdi are connected, a composite waveform consisting of transmit waveform from the transmitting de vice and parity error signal from the txdi pin, is generated. 4. bits cnt3 to cnt0 in the tcspr register select s no division (n = 0) or divide-by-2n (n = 1 to 15). set to 0 by an interrupt request a cknowledgement or by program 1 0 1 0 1 0 1 0 1 0 1 0 m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 249 of 352 rej09b0385-0100 figure 17.34 sim interface connection 17.1.6.1 parity error si gnal output function when the uiere bit in the uic1 register (i = 0 to 4) is set to 1 (error signal output), the parity error signal output is enabled. the parity error signal is output when a parity error is detected upon receiving data, and an ?l? signal is output from the txdi pin in the timing show n in figure 17.35. if the uirb register is read while a parity error signal is output, the per bit in the uirb register is set to 0 (parity error not occurred) and the txdi pin level becomes back to ?h?. to determine whether the parity error signal is output or not, read the port that shares a pin with the rxdi pin in the transmission complete interrupt routine. figure 17.35 parity error signal output timing mcu txdi rxdi i = 0 to 4 sim card note: 1. connect the txdi and rxdi pins and pull up these pins. receive operation complete flag i = 0 to 4 st: start bit p: even parity bit sp: stop bit rxdi st d1 d3 d4 d5 d6 d2 d7 txdi p d0 sp "h" "l" 0 1 "h" "l" hi-z the above applies under direct format conditions: - uimr register: pry bit = 1 (odd parity) - uic0 register: uform bit = 0 (lsb first) - uic1 register: uilch bit = 0 (not inverted) m32c/8a group 17. serial interfaces rev.1.00 jul 15, 2007 page 250 of 352 rej09b0385-0100 17.1.6.2 formats 17.1.6.2.1 direct format when data is transmitted, data set in the uitb register (i = 0 to 4) is transmitted with even parity, starting from d0 . when data is received, received data is stored into the uirb register , starting from d0. a parity error is determined with even parity. set the bits as follows to transmit or receive in the direct format. ? set the prye bit in the uimr register to 1 (parity enabled). ? set the pry bit in the uimr register to 1 (even parity). ? set the uform bit in the uic0 register to 0 (lsb first). ? set the uilch bit in the uic1 register to 0 (not inverted). 17.1.6.2.2 inverse format when data is transmitted, values set in the uitb register are logically inverted. the data with the inverted values is transmitted with odd pari ty, starting from d7. when data is received, received data is logically inverted to be stored into the uirb register, starting from d7. a parity error is determined with odd parity. set the bits as follows to transmit or receive in the inverse format. ? set the prye bit to 1 (parity enabled). ? set the pry bit to 0 (odd parity). ? set the uform bit to 1 (msb first). ? set the uilch bit to 1 (inverted). figure 17.36 sim interface formats (1) direct format d1 d3 d4 d5 d6 d2 d7 p d0 i = 0 to 4 p: even parity "h" "l" (2) inverse format txdi p p: odd parity "h" "l" d1 d3 d4 d5 d6 d2 d7 d0 txdi st sp sp st st: start bit sp: stop bit m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 251 of 352 rej09b0385-0100 18. a/d converter m32c/8a group has one 10-bit successive approximation a/d converter with a capacitance coupled amplifier. the results of a/d conversion are stored into the ad0i regist ers (i = 0 to 7) corresponding to the selected pins. when using dmac operating mode, the conversion results are stored only into the ad00 register. table 18.1 lists specifications of the a/ d converter. figure 18.1 shows a block diagram of the a/d converter. figures 18.2 to 18.6 show registers asso ciated with th e a/d converter. this section is described in the 144-pin package as an example. pins an15_0 to an15_7 are not provided in the 100-pin package. note m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 252 of 352 rej09b0385-0100 table 18.1 a/d converter specifications notes: 1. the ad frequency must be16 mhz or lower when vcc1 = 4.2 to 5.5 v. the ad frequency must be10 mhz or lower when vcc1 = 3.0 to 5.5 v. without the sample and hold function, the ad frequency must be 250 khz or higher. with the sample and hold function, the ad frequency must be 1 mhz or higher. 2. avcc = vcc1 ad input (an_0 to an_7, an 15_0 to an15_7, anex0, anex1) vcc1 item specification a/d conversion method successive approximation (with capacitance coupled amplifier) analog input voltage 0 v to avcc (vcc1) operating clock ad (1) fad, fad/2, fad/3, fad/4, fad/6, fad/8 resolution selectable from 8 bits or 10 bits operating modes ? one-shot mode ? repeat mode ? single sweep mode ? repeat sweep mode 0 ? repeat sweep mode 1 ? multi-port single sweep mode ? multi-port repeat sweep mode 0 analog input pins (2) 144 pin package: 18 pins 8 pins each for an (an_0 to an_7), an15 (an15_0 to an15_7) 2 extended input pins (anex0 and anex1) 100 pin package: 10 pins 8 pins for an (an_0 to an_7) 2 extended input pins (anex0 and anex1) a/d conversion start condition ? software trigger the adst bit in the ad0con0 register is set to ?1? (a/d conversion starts). ? external trigger (retrigger is enabled) when the falling edge is detected at the adtrg pin after the adst bit is set to 1. ? hardware trigger (retrigger is enabled) timer b2 interrupt request of the three-phase motor control timer function (after the ictb2 register completes counting) is generated after the adst bit is set to 1. conversion rate per pin ? without sample and hold function 8-bit resolution: 49 ad cycles, 10-bit resolution: 59 ad cycles ? with sample and hold function 8-bit resolution: 28 ad cycles, 10-bit resolution: 33 ad cycles m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 253 of 352 rej09b0385-0100 figure 18.1 a/d converter block diagram successive conversion register notes: 1. these pins are provi ded in the 144-pin package only. 2. avcc = vcc1, ad input (an_0 to an_7, an15_0 to an15_7, anex0, anex1) vcc1 timer b2 interrupt request (after ictb2 register completes counting) of the three-phase control timer function 0 1 trg0 bit in ad0con2 register trg bit in ad0con0 register 000 010 001 011 100 101 110 111 an15_0 an15_2 an15_1 an15_3 an15_4 an15_5 an15_6 an15_7 000 010 001 011 100 101 110 111 an_0 an_2 an_1 an_3 an_4 an_5 an_6 an_7 1x x1 ad00 register comparator ad07 register ad06 register ad05 register ad04 register ad03 register ad02 register ad01 register resistor ladder ad0con0 register ad0con1 register ad0con2 register ad0con3 register ad0con4 register bits ch2 to ch0 in ad0con0 register p9_6 anex1 p9_5 anex0 p10 (2) fad 1/2 1/2 1/2 cks1 bit in ad0con1 register ad 1 0 1 0 1 0 1 adtrg bits aps1 and aps0 in ad0con2 register 00 01 11 01 p15 (1, 2) 1 0 bits ch2 to ch0 in ad0con0 register decoder bits opa1 and opa0 in ad0con1 register software trigger 0 1/3 00 cks2 bit in ad0con3 register cks0 bit in ad0con0 register adst bit start trigger m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 254 of 352 rej09b0385-0100 figure 18.2 ad0con0 register b7 b6 b5 b4 b1 b2 b3 symbol ad0con0 address 0396h after reset 00h b0 function bit symbol bit name rw trg cks0 a/d operating mode select bits 0 (2) frequency select bit 0 rw rw rw rw md1 rw md0 trigger select bit a/d conversion start bit adst a/d0 control register 0 (1) ch1 rw rw ch2 b2 b1 b0 0 0 0: ani_0 0 0 1: ani_1 0 1 0: ani_2 0 1 1: ani_3 1 0 0: ani_4 1 0 1: ani_5 1 1 0: ani_6 1 1 1: ani_7 (i = none, 15) analog input pin select bits (2, 3) ch0 rw when the mss bit in the ad0con3 register = 0 b4 b3 0 0: one-shot mode 0 1: repeat mode 1 0: single sweep mode 1 1: repeat sweep mode 0, repeat sweep mode 1 when the mss bit in the ad0con3 register = 1 b4 b3 0 0: 0 1: 1 0: multi-port single sweep mode 1 1: multi-port repeat sweep mode 0 0: software trigger 1: external trigger, hardware trigger (4) 0: a/d conversion stops 1: a/d conversion starts (4) (note 5) notes: 1. if the ad0con0 register is rewritten duri ng a/d conversion, the conver sion result will be incorrect. 2. analog input pins must be configured again after an a/d operating mode is changed. 3. bit ch2 to ch0 is enabled in one-shot mode and repeat mode. 4. to set the trg bit to 1, select a trigger source usi ng the trg0 bit in the ad0con2 register. then, set the adst bit to 1 after the trg bit is set to 1. 5. ad frequency must be 16 mhz or below when vcc1 = 4.2 to 5.0v. ad frequency must be 10 mhz or below when vcc1 = 3.0 to 5.0v. ad is selected by the combination of the cks0 bit, the cks1 in the ad0con1 register, and the cks2 bit in the ad0con3 register. cks2 bit in ad0con3 register cks0 bit in ad0con0 register ad cks1 bit in ad0con1 register 0 0 fad divided by 4 0 1 1 0 1 0 1 1 0 fad divided by 3 fad divided by 2 fad fad divided by 8 fad divided by 6 do not set to these values. m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 255 of 352 rej09b0385-0100 figure 18.3 ad0con1 register b7 b6 b5 b4 b1 b2 b3 a/d0 control register 1 (1) symbol ad0con1 address 0397h bit symbol rw after reset 00h notes: 1. if the ad0con1 register is rewritten duri ng a/d conversion, the conversion result will be incorrect. 2. bits scan1 and scan0 are enabled in single sweep m ode, repeat sweep mode 0, 1, multi-port single sweep mode, and multi- port repeat sweep mode 0. 3. these are prioritized pins used fo r a/d conversion when the md2 bit is set to 1. 4. when the mss bit in the ad0con3 register is set to 1 (multi-port sweep mode used); -set bits scan1 and scan0 to 11b -set the md2 bit to 0 -set bits opa1 and opa0 to 00b. 5. refer to the note for the cks0 bit in the ad0con0 register. 6. bits opa1 and opa0 can be set to 01b or 10b in one-shot mode and repeat mode. set these bits to 00b or 11b in other modes. 7. do not set the vcut bit to 0 during a/d conversion. ev en if the vcut bit is set to 0, vref remains connected to the d/ a converter. 8. when the vcut bit is set to 1 from 0, wait for 1 s or more to start the a/d conversion. b0 rw md2 vcut rw bits cks1 rw rw rw opa0 opa1 scan0 scan1 rw rw rw bit name resolution select bit a/d operating mode select bit 1 (4) frequency select bit 1 vref connection bit (8) extended input pin function select bits (4, 6) a/d sweep pin select bits (2) function 0: 8-bit mode 1: 10-bit mode (note 5) 0: other than repeat sweep mode 1 1: repeat sweep mode 1 b7 b6 0 0: anex0 and anex1 are not used 0 1: signal applied to anex0 is a/d converted 1 0: signal applied to anex1 is a/d converted 1 1: external op-amp connection 0: vref not connected (7) 1: vref connected single sweep mode and repeat sweep mode 0 b1 b0 0 0: ani_0, ani_1 (i = none, 15) 0 1: ani_0 to ani_3 1 0: ani_0 to ani_5 1 1: ani_0 to ani_7 repeat sweep mode 1 (3) b1 b0 0 0: ani_0 0 1: ani_0, ani_1 1 0: ani_0 to ani_2 1 1: ani_0 to ani_3 multi-port single sweep mode and multi-port repeat sweep mode 0 (4) set to 11b. m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 256 of 352 rej09b0385-0100 figure 18.4 ad0con2 register b7 0 0 b6 b5 b4 b1 b2 b3 symbol ad0con2 address 0394h after reset xx0x x000b b0 function bit symbol bit name rw ? (b7-b6) reserved bits ? rw rw ? (b4-b3) external trigger source select bit trg0 a/d0 control register 2 (1) aps0 rw rw aps1 when the mss bit in the ad0con3 register = 0 b2 b1 0 0: an_0 to an_7, anex0, anex1 0 1: an15_0 to an15_7 (2) 1 0: 1 1: when the mss bit in the ad0con3 register = 1 set to 01b. analog input port select bits smp rw 0: adtrg selected 1: timer b2 interrupt request of the three-phase motor control timer function (after the ictb2 register completes counting) selected set to 0. read as undefined value. notes: 1. if the ad0con2 register is rewritten during a/d conversion, the conversion result will be incorrect. 2. in the 100-pin package, do not set to 01b. a/d conversion method select bit 0: without sample and hold 1: with sample and hold unimplemented. write 0. read as undefined value. do not set to these values. m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 257 of 352 rej09b0385-0100 figure 18.5 ad0con3 register b7 0 0 0 b6 b5 b4 b1 b2 b3 a/d0 control register 3 (1, 2) symbol ad0con3 address 0395h bit symbol rw dus after reset xxxx x000b rw notes: 1. if the ad0con3 register is rewritten during a/d conversion, the conversi on result will be incorrect. 2. the ad0con3 register may return an incorrect value if read during a/d conversion. it must be read or written after the a/d conversion stops. 3. when the mss bit is set to 1; -set the dus bit to 1 and configure dmac. -set bits md1 and md0 in the ad0con0 register to 10b or 11b. -set bits scan1 and scan0 in the ad0con1 re gister to 11b, the md2 bit to 0, bits opa1 and opa0 to 00b. -set bits aps1 and aps0 in the ad0con2 register to 01b. -set bits mps11 and mps10 to 01b. 4. refer to the note for the cks0 bit in the ad0con0 register. 5. bits msf1 and msf0 are enabled when the mss bit is set to 1. when the mss bit is set to 0, a read from these bits retu rns an undefined value. b0 mss rw ro cks2 msf0 msf1 rw ro ? (b7-b5) rw bit name multi-port sweep status flags (5) function b4 b3 0 0: an_0 to an_7 0 1: an15_0 to an15_7 1 0: 1 1: reserved bits set to 0. read as undefined value. multi-port sweep mode select bit dmac operating mode select bit 0: multi-port sweep mode not used 1: multi-port sweep mode used (3) 0: dmac operating mode not used 1: dmac operating mode used frequency select bit 2 (note 4) do not set to these values. m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 258 of 352 rej09b0385-0100 figure 18.6 ad0con4 register, ad00 to ad07 registers b7 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol ad0con4 address 0392h after reset xxxx 00xxb b0 function bit symbol bit name rw ? (b7-b4) reserved bits rw a/d0 control register 4 (1) mps10 rw rw mps11 b3 b2 0 0: (note 3) 0 1: an_0 to an_7, an15_0 to an15_7 1 0: 1 1: multi-port sweep port select bits (2) ? (b1-b0) rw set to 0. read as undefined value. notes: 1. if the ad0con4 register is rewritten during a/d conversion, the conversion result will be incorrect. 2. set bits mps11 and mps10 to 00b in the 100-pin package. 3. when the mss bit in the ad0con3 register is set to 0 (multi-port sweep mode not used), set bits mps11 and mps10 to 00b. when the mss bit is set to 1 (multi-port sweep mode used), set bits mps11 and mps10 to 01b. reserved bits set to 0. read as undefined value. b15 b7 b8 a/d0 register i (1, 2, 3, 4) (i = 0 to 7) symbol ad00 ad01 to ad03 ad04 to ad06 ad07 address 0381h - 0380h 0383h - 0382h, 0385h - 0384h, 0387h - 0386h 0389h - 0388h, 038bh - 038ah, 038dh - 038ch 038fh - 038eh after reset b0 00000000 xxxxxxxxb 00000000 xxxxxxxxb 00000000 xxxxxxxxb 00000000 xxxxxxxxb function rw ro notes: 1. when the ad0i register is read by program in dmac operating mode, the conversion result is incorrect. 2. if the next a/d conversion result is stored before r eading the previous result in the ad0i register, the result will be incorrect. 3. only ad00 register is enabled in dmac oper ating mode. the contents of other registers are undefined. 4. when using both dmac operating mode and 10-bit mode, select a 16-bit transfer for dmac. ro ro in 10-bit mode: 2 high-order bits of a/d conversion result in 8-bit mode: read as 0. 8 low-order bits of a/d conversion result reserved bits. read as 0. 0 0 0 0 0 0 do not set to these values. m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 259 of 352 rej09b0385-0100 if analog input shares the pin with other peripheral func tion inputs, a through current may flow to the peripheral function inputs when an intermediate voltage is applied to the pin. to prevent through current, set the control bit for the corresponding pin to 1, and other peripheral inputs are disconnected. table 18.2 analog input pin setting 18.1 mode descriptions the a/d converter has seven different modes. table 18.3 lists settings for these modes. table 18.3 mode settings ? : can be either 0 or 1. pin function control bit psc register psl3 register p9_5 anex0 ? psl3_5 = 1 p9_6 anex1 ? psl3_6 = 1 p10_4 an_4 psc_7 = 1 ? p10_5 an_5 ? p10_6 an_6 ? p10_7 an_7 ? mode ad0con0 register ad0con1 register ad0con3 register md1 bit md0 bit md2 bit mss bit dus bit one-shot mode 0 0 0 0 ? repeat mode 0 1 0 0 ? single sweep mode 1 0 0 0 ? repeat sweep mode 0 1 1 0 0 ? repeat sweep mode 1 1 1 1 0 ? multi-port single sweep mode 10 0 11 multi-port repeat sweep mode 0 11 0 11 m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 260 of 352 rej09b0385-0100 18.1.1 one-shot mode in one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. table 18.4 lists specifications of one-shot mode. table 18.4 one-shot mode specifications item specification function analog voltage applied to a selected pin is converted once analog input pins select one pin from an_0 to an_7, an15_0 to an15_7, anex0, or anex1 the following register settings determine which pin is used: ? bits ch2 to ch0 in the ad0con0 register ? bits opa1 and opa0 in the ad0con1 register ? bits aps1 and aps0 in the ad0con2 register start condition software trigger is selected. (trg bit in the ad0con0 register = 0): ? the adst bit in the ad0con0 register is set to 1 (a/d conversion starts) external trigger, hardware trigger is selected (trg bit = 1): ? trg0 bit in the ad0con2 register = 0 the falling edge is detected on the adtrg pin after the adst bit is set to 1 ? trg0 bit = 1 timer b2 interrupt request of three-phase motor control timer function (after the ictb2 register completes counting) is generated after the adst bit is set to 1. stop condition ? a/d conversion is completed (the adst bit becomes 0 when software trigger is selected). ? set the adst bit to 0 by program (a/d conversion stops). interrupt request generation timing when the a/d conversion is completed read of a/d conversion result ? dmac operating mode is not used (dus bit in the ad0con3 register = 0): read the ad0j register (j = 0 to 7) corresponding to a selected pin by program. ? dmac operating mode is used (dus bit = 1): a/d conversion result is stored into the ad00 register after a/d conversion is completed. then, dmac transfers the data from the ad00 register to a given memory space. (refer to 13. dmac for dmac settings) m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 261 of 352 rej09b0385-0100 18.1.2 repeat mode in repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. table 18.5 lists specifications of repeat mode. table 18.5 repeat mode specifications item specification function analog voltage applied to a selected pin is repeatedly converted analog input pins select one pin from an_0 to an_7, an15_0 to an15_7, anex0, or anex1 the following register settings determine which pin is used: ? bits ch2 to ch0 in the ad0con0 register ? bits opa1 and opa0 in the ad0con1 register ? bits aps1 and aps0 in the ad0con2 register start condition software trigger is selected. (trg bit in the ad0con0 register = 0): ? the adst bit in the ad0con0 register is set to 1 (a/d conversion starts) external trigger, hardware trigger is selected (trg bit = 1): ? trg0 bit in the ad0con2 register = 0 the falling edge is detected on the adtrg pin after the adst bit is set to 1 ? trg0 bit = 1 timer b2 interrupt request of three-phase motor control timer function (after the ictb2 register completes counting) is generated after the adst bit is set to 1. stop condition set the adst bit register to 0 (a/d conversion stops) interrupt request generation timing ? dmac operating mode is not used (dus bit in the ad0con3 register = 0): interrupt request is not generated. ? dmac operating mode is used (dus bit = 1): interrupt request is generated every time each a/d conversion is completed. read of a/d conversion result ? dmac operating mode is not used (dus bit = 0): read the ad0j register (j = 0 to 7) corresponding to a selected pin by program. ? dmac operating mode is used (dus bit = 1): a/d conversion result is stored into the ad00 register after a/d conversion is completed. then, dmac transfers the data from the ad00 register to a given memory space. (refer to 13. dmac for dmac settings) m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 262 of 352 rej09b0385-0100 18.1.3 single sweep mode in single sweep mode, analog voltage that is applied to multiple selected pins is converted to a digital code once for each pin. table 18.6 lists specifications of single sweep mode. table 18.6 single sweep mode specifications item specification function analog voltage applied to selected pins is converted once for each pin analog input pins select one of the following. ? 2 pins (ani_0 and ani_1) (i = none, 15) ? 4 pins (ani_0 to ani_3) ? 6 pins (ani_0 to ani_5) ? 8 pins (ani_0 to ani_7) the following register settings determine which pins are used: ? bits scan1 and scan0 in the ad0con1 register ? bits aps1 and aps0 in the ad0con2 register start condition software trigger is selected. (trg bit in the ad0con0 register = 0): ? the adst bit in the ad0con0 register is set to 1 (a/d conversion starts) external trigger, hardware trigger is selected (trg bit = 1): ? trg0 bit in the ad0con2 register = 0 the falling edge is detected on the adtrg pin after the adst bit is set to 1 ? trg0 bit = 1 timer b2 interrupt request of three-phase motor control timer function (after the ictb2 register completes counting) is generated after the adst bit is set to 1. stop condition ? a sequence of a/d conversions is completed (the adst bit becomes 0 when software trigger is selected) ? set the adst bit to 0 by program (a/d conversion stops) interrupt request generation timing ? dmac operating mode is not used (dus bit in the ad0con3 register = 0): interrupt request is generated after a sequence of a/d conversions is completed. ? dmac operating mode is used (dus bit = 1): interrupt request is generated every time each a/d conversion is completed read of a/d conversion result ? dmac operating mode is not used (dus bit = 0): read the ad0j register (j = 0 to 7) corresponding to a selected pin by program. ? dmac operating mode is used (dus bit = 1): a/d conversion result is stored into the ad00 register after a/d conversion is completed. then, dmac transfers the data from the ad00 register to a given memory space. (refer to 13. dmac for dmac settings) m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 263 of 352 rej09b0385-0100 18.1.4 repeat sweep mode 0 in repeat sweep mode 0, analog voltage applied to multip le selected pins is repeatedly converted to a digital code. table 18.7 lists specifications of repeat sweep mode 0. table 18.7 repeat sweep mode 0 specifications item specification function analog voltage applied to selected pins is repeatedly converted analog input pins select one of the following. 2 pins (ani_0 and ani_1) (i = none, 15) 4 pins (ani_0 to ani_3) 6 pins (ani_0 to ani_5) 8 pins (ani_0 to ani_7) the following register settings determine which pins are used: ? bits scan1 and scan0 in the ad0con1 register ? bits aps1 and aps0 in the ad0con2 register start condition software trigger is selected. (trg bit in the ad0con0 register = 0): ? the adst bit in the ad0con0 register is set to 1 (a/d conversion starts) external trigger, hardware trigger is selected (trg bit = 1): ? trg0 bit in the ad0con2 register = 0 the falling edge is detected on the adtrg pin after the adst bit is set to 1 ? trg0 bit = 1 timer b2 interrupt request of three-phase motor control timer function (after the ictb2 register completes counting) is generated after the adst bit is set to 1. stop condition set the adst bit register to 0 (a/d conversion stops) interrupt request generation timing ? dmac operating mode is not used (dus bit in the ad0con3 register = 0): interrupt request is not generated ? dmac operating mode is used (dus bit = 1): interrupt request is generated every time each a/d conversion is completed read of a/d conversion result ? dmac operating mode is not used (dus bit = 0): read the ad0j register (j = 0 to 7) corresponding to a selected pin by program. ? dmac operating mode is used (dus bit = 1): a/d conversion result is stored into the ad00 register after a/d conversion is completed. then, dmac transfers the data from the ad00 register to a given memory space. (refer to 13. dmac for dmac settings) m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 264 of 352 rej09b0385-0100 18.1.5 repeat sweep mode 1 in repeat sweep mode 1, analog voltage applied to ei ght pins, prioritizing one to four pins, is repeatedly converted to a digital code. table 18.8 lists specifications of repeat sweep mode 1. table 18.8 repeat sweep mode 1 specification item specification function analog voltage applied to 8 selected pins, prioritizing one to four pins, is repeatedly converted. analog input pins ani_0 to ani_7 (8 pins are selected from these pins) (i = none, 15) prioritized pins select one of the following. ? single pin (ani_0) ? 2 pins (ani_0 and ani_1) ? 3 pins (ani_0 to ani_2) ? 4 pins (ani_0 to ani_3) the following register settings determine which pins are used: ? bits scan1 and scan0 in the ad0con1 register ? bits aps1 and aps0 in the ad0con2 register start condition software trigger is selected. (trg bit in the ad0con0 register = 0): ? the adst bit in the ad0con0 register is set to 1 (a/d conversion starts) external trigger, hardware trigger is selected (trg bit = 1): ? trg0 bit in the ad0con2 register = 0 the falling edge is detected on the adtrg pin after the adst bit is set to 1 ? trg0 bit = 1 timer b2 interrupt request of three-phase motor control timer function (after the ictb2 register completes counting) is generated after the adst bit is set to 1. (retrigger of external trigger is invalid) stop condition set the adst bit is set to 0 (a/d conversion stops) interrupt request generation timing ? dmac operating mode is not used (dus bit in the ad0con3 register = 0): interrupt request is not generated. ? dmac operating mode is used (dus bit = 1): interrupt request is generated every time each a/d conversion is completed. read of a/d conversion result ? dmac operating mode is not used (dus bit = 0): read the ad0j register (j = 0 to 7) corresponding to a selected pin by program. ? dmac operating mode is used (dus bit = 1): a/d conversion result is stored into the ad00 register after a/d conversion is completed. then, dmac transfers the data from the ad00 register to a given memory space. (refer to 13. dmac for dmac settings) m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 265 of 352 rej09b0385-0100 figure 18.7 transition diagram of pins used in a/d conversion in repeat sweep mode 1 ani_0 ani_1 ani_2 ani_3 ani_4 ani_5 ani_6 ani_7 ani_0 ani_1 ani_2 ani_3 ani_4 ani_5 ani_6 ani_7 when ani_0 is prioritized (single pin) time when ani_0 and ani_1 are prioritized (2 pins) ani_0 ani_1 ani_2 ani_3 ani_4 ani_5 ani_6 ani_7 when ani_0 to ani_2 are prioritized (3 pins) ani_0 ani_1 ani_2 ani_3 ani_4 ani_5 ani_6 ani_7 when ani_0 to ani_3 are prioritized (4 pins) : a/d conversion i = none, 15 m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 266 of 352 rej09b0385-0100 18.1.6 multi-port single sweep mode in multi-port single sweep mode, analog voltage applied to 16 selected pins is converted to a digital code once for each pin. set the dus bit in the ad0con3 register to 1 (dmac operating mode enabled). table 18.9 lists specifications of multi-port single sweep mode. table 18.9 multi-port single sweep mode specifications item specification function analog voltage applied to the 16 selected pins is repeatedly converted once for each pin in the following order: an_0 to an_7 an15_0 to an15_7 analog input pins ? an_0 an_1 . . . an_7 an15_0 an15_1 . . . an15_7 the following register settings determine which pins are used: bits mps11 and mps10 in the ad0con4 register start condition software trigger is selected. (trg bit in the ad0con0 register = 0): ? the adst bit in the ad0con0 register is set to 1 (a/d conversion starts) external trigger, hardware trigger is selected (trg bit = 1): ? trg0 bit in the ad0con2 register = 0 the falling edge is detected on the adtrg pin after the adst bit is set to 1 ? trg0 bit = 1 timer b2 interrupt request of three-phase motor control timer function (after the ictb2 register completes counting) is generated after the adst bit is set to 1. stop condition ? a sequence of a/d conversions is completed (the adst bit becomes 0 when software trigger is selected) ? set the adst bit to 0 by program (a/d conversion stops) interrupt request generation timing an interrupt request is generated every time each a/d conversion is completed (set the dus bit in the ad0con3 register to 1) read of a/d conversion result a/d conversion result is stored into the ad00 register after a/d conversion is completed. then, dmac transfers the data from the ad00 register to a given memory space. refer to 13. dmac for dmac settings. (set the dus bit in the ad0con3 register to 1) m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 267 of 352 rej09b0385-0100 18.1.7 multi-port rep eat sweep mode 0 in multi-port repeat sweep mode 0, analog voltage that is applied to 16 selected pins is repeatedly converted to a digital code. set the dus bit in the ad0con3 register to 1 (dmac operating mode enabled). table 18.10 lists specifications of multi-port repeat sweep mode 0. table 18.10 multi-port repeat sweep mode 0 specifications item specification function analog voltage applied to the 16 selected pins is repeatedly converted in the following order: an_0 to an_7 an15_0 to an15_7 analog input pins ? an_0 an_1 . . . an_7 an15_0 an15_1 . . . an15_7 the following register settings determine which pins are used: bits mps11 and mps10 in the ad0con4 register start condition software trigger is selected. (trg bit in the ad0con0 register = 0): ? the adst bit in the ad0con0 register is set to 1 (a/d conversion starts) external trigger, hardware trigger is selected (trg bit = 1): ? trg0 bit in the ad0con2 register = 0 the falling edge is detected on the adtrg pin after the adst bit is set to 1 ? trg0 bit = 1 timer b2 interrupt request of three-phase motor control timer function (after the ictb2 register completes counting) is generated after the adst bit is set to 1. stop condition set the adst bit is set to 0 (a/d conversion stops) interrupt request generation timing an interrupt request is generated every time each a/d conversion is completed (set the dus bit in the ad0con3 register to 1) read of a/d conversion result a/d conversion result is stored into the ad00 register after a/d conversion is completed. then, dmac transfers the data from the ad00 register to a given memory space. refer to 13. dmac for dmac settings (set the dus bit in the ad0con3 register to 1) m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 268 of 352 rej09b0385-0100 18.2 functions 18.2.1 resolution the bits bit in the ad0con1 register determines the re solution. when the bits bit is set to 1 (10-bit mode), the a/d conversion result is stored into bits 9 to 0 in the ad 0i register (i = 0 to 7). when the bits bit is set to 0 (8-bit mode), the a/d conversion result is stored into bits 7 to 0 in the ad0i register. 18.2.2 sample and hold when the smp bit in the ad0con2 register is set to 1 (with sample and hold), the a/d conversion rate per pin increases to 28 ad cycles for 8-bit resolution and 33 ad cycles for 10-bit resolution. the sample and hold function is available in all operatin g modes. start a/d conversion after se lecting whether the sample and hold circuit is used or not. 18.2.3 trigger select function the trg bit in the ad0con0 register and the trg0 bit in the ad0con2 register determine a trigger to start a/d conversion. table 18.11 lists setting values for the trigger select function. table 18.11 trigger select function setting values notes: 1. a/d conversion starts when the adst bit is set to 1 (a/d conversion starts) and a trigger is generated. 2. a/d conversion starts over from the beginning, if an external trigger or a hardware trigger is inserted during a/d conversion. (a/d conversion in progress is aborted.) 18.2.4 dmac operating mode dmac operating mode is available in all operating modes. to select multi-port single sweep mode or multi- port repeat sweep mode 0, dmac operating mode must be used. when the dus bit in the ad0con3 register is set to 1 (dmac operating mode used), all a/d conver sion results are stored in to the ad00 register. dmac transfers the result from the ad00 regi ster to a given memory space every time a/d conversion on a single pin is completed. 8-bit dma transfer must be selected for 8-bit resolution and 16-bit dma transfer for 10-bit resolution. refer to 13. dmac for dmac instructions. when using dmac operating mode in single sweep mode , repeat sweep mode 0, re peat sweep mode 1, multi- port single sweep mode, or multi-port repeat sweep mode 0, do not generate an exte rnal retrigger or hardware retrigger. 18.2.5 extended analog input pins in one-shot mode and repeat mode, the anex0 pin or anex1 pin can be used as the analog input pin. these pins can be selected using bits opa1 and opa0 in the ad0con1 register. the a/d conversion result for anex0 input is stored into the ad00 register, and for anex1 input into the ad01 register. both results are stored into the ad00 register when the dus bit in the ad0con3 register is set to 1 (dmac operating mode used). set bits aps1 and aps0 in the ad0con2 register to 00b (an_0 to an_7, anex0, anex1) and the mss bit in the ad0con3 register to 0 (multi-port sweep mode not used). bit and setting trigger ad0con0 register ad0con2 register trg = 0 ? software trigger a/d conversion starts when the adst bit in the ad0con0 register is set to 1 trg = 1 (1) trg0 = 0 external trigger (2) falling edge of a signal applied to adtrg trg0 = 1 hardware trigger (2) timer b2 interrupt request of three-phase motor control timer function (after the ictb2 register completes counting) m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 269 of 352 rej09b0385-0100 18.2.6 external operating amplif ier (op-amp) connection mode in external op-amp connection mode, multiple analog vo ltage can be amplified by one external op-amp using extended analog input pins, anex0 and anex1. when bits opa1 and opa0 are set to 11b (externa l op-amp connection), voltage applied to pins an_0 to an_7 are output from the anex0. amplify this output signal by external op-amp and apply it to the anex1. analog voltage applied to anex1 is co nverted to a digital code and the a/d conversion result is stored into the corresponding ad0i register (i = 0 to 7). the a/ d conversion rate varies depending on the response characteristics of the external op-amp. the anex0 pin cannot be connected to the anex1 pin directly. set bits aps1 and aps0 in the ad0con2 register to 00b (an_0 to an_7, anex0, anex1). figure 18.8 shows a connection example of external op-amp connection mode. table 18.12 extended analog input pin settings figure 18.8 connection example in external op-amp connection mode 18.2.7 power consumption reduce function when not using the a/d converter, the vcut bit in the ad0con1 register can disconnect the resistor ladder of the a/d converter from the reference voltage input pin (vref). as a result, power consumption can be reduced by shutting off any current flow into the resistor ladder from the vref pin. when using the a/d converter, set the vcut bit to 1 (vref connected) prior to setting the adst bit in the ad0con0 register to 1 (a/d conversion starts). do not set the vcut bit to 0 (vref not connected) during a/d conversion. even if the vcut bit is set to 0, vref remains connected to the d/a converter. ad0con1 register anex0 function anex1 function opa1 bit opa0 bit 0 0 not used not used 0 1 p9_5 as an analog input not used 1 0 not used p9_6 as an analog input 1 1 output to external op-amp input from external op-amp successive conversion register an_0 an_2 an_1 an_3 an_4 an_5 an_6 an_7 analog input anex1 external op-amp anex0 resistor ladder bits aps1 and aps0 in the ad0con2 register 00b comparator m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 270 of 352 rej09b0385-0100 18.3 read from the ad0i register (i = 0 to 7) use the following procedure to read the ad0i register by program. ? in one-shot mode and single sweep mode: ensure that the a/d conversion is completed before readin g the corresponding ad0i register. the ir bit in the ad0ic register becomes 1 when th e a/d conversion is completed. ? in repeat mode, repeat sweep mode 0, and repeat sweep mode 1: read the ad0i register after setting the cpu clock as follows. (1) set the cm07 bit in the cm0 register to 0 (clock selected by the cm21 bit divided by the mcd register). (2) set the mcd register to 12h (no division). 18.4 output impedance of sensor e quivalent circuit unde r a/d conversion to take full advantage of the a/d converter performan ce, internal capacitor (c) charge shown in figure 18.9 must be completed within the specified period (t) as sampling time. output impedance of the sensor equivalent circuit (r0) is determined by the following equation: where: vc = internal capacitor voltage r = internal resistance of the mcu x = accuracy (error) of the a/d converter y = resolution (1024 in 10-bit mode, and 256 in 8-bit mode) figure 18.9 shows a connection example of analog input pin and external sensor equivalent circuit. in the following example, the impeda nce r0 is obtained from the equation above when vc changes from 0 to vin-(1/1024)vin within the time (t), if the difference between vin an d vc becomes 1lsb. (1/1024) means that a/d accuracy dr op, due to insufficient capacitor charge, is held to 1lsb at time of a/d conversion in the 10-bit mode. actual error, however, is the value of absolute accuracy added to 1lsb. when ad = 10 mhz, t = 0.3 s in a/d conversion with the sample and hold function. output impedance (r0) enough to complete charging the capacitor (c) within the time (t) is determined by the following equation: thus, the allowable output impedance r0 of the se nsor equivalent circuit, maki ng the accuracy (error) 1lsb or less, is approximately 3.8 k maximum. vc vin 1 e 1 cr0 r + () ---------------------------- t ? ? ?? ?? ?? = when t = t, vc vin x y --- -vin ? vin 1 x y --- - ? ?? ?? == e 1 cr0 r + () ---------------------------- t ? x y --- - = 1 cr0 r + () --------------------------- -t ? x y --- - ln = r0 t c x y --- - ln -------------- ? r ? = 3.8 10 3 r0 0.3 10 6 ? 7.5 10 12 ? 1 1024 ------------ - ln ? ---------------------------------------------------- ? 2.0 10 3 ? = using t = 0.3 s, r = 2.0 k , c = 7.5 pf, x = 1, y = 1024, ? m32c/8a group 18. a/d converter rev.1.00 jul 15, 2007 page 271 of 352 rej09b0385-0100 figure 18.9 analog input pin and exte rnal sensor equivalent circuit sensor equivalent circuit mcu r0 vin vc r (2.0 k ) c (7.5 pf) sampling time sample and hold is enabled : sample and hold is disabled : 3 ad 2 ad m32c/8a group 19. d/a converter rev.1.00 jul 15, 2007 page 272 of 352 rej09b0385-0100 19. d/a converter the d/a converter consis ts of two independent 8-bit r-2r ladder d/a converter circuits. digital code is converted to an analog voltage every time a value to be converted is written to the corresponding dai register (i = 0, 1). the daie bit in the dacon register determines whether the d/a conversion result is output or not. when the daie bit is set to 1 (input enabled), the corresponding port cannot be pulled up. when the d/a converter is not used, set the dai register to 00h and the daie bit to 0 (output disabled). output analog voltage ( v ) is obtained from the value n (n = decimal) set in the dai register. vref: reference voltage (vref remains connected even if the vcut bit in the ad0con1 register is set to 0) table 19.1 lists specifications of the d/a converter. figure 19.1 shows a block diagram of the d/a converter. table 19.2 lists pin settings of da0 and da1. figure 19.2 show s registers associated with the d/a converter. figure 19.3 shows a d/a converter equivalent circuit. table 19.1 d/a converter specifications figure 19.1 d/a converter block diagram table 19.2 pin settings notes: 1. set the ps3 register after setting other registers. 2. set the pd9 or ps3 register immediately after the prc2 bit in the prcr register is set to 1 (write enable). do not generate an interrupt or a dma or dmacii transfer between these two instructions. item specification d/a conversion method r-2r resolution 8 bits analog output pin 2 channels port function bit setting pd9 register (2) psl3 register ps3 register (1)(2) p9_3 da0 output pd9_3=0 psl3_3=1 ps3_3=0 p9_4 da1 output pd9_4=0 psl3_4=1 ps3_4=0 v = 256 vref x n (n = 0 to 255) da0e, da1e: bits in the dacon register low-order bits of data bus r-2r resistor ladder da1 register r-2r resistor ladder da0e da1e da1 da0 1 1 0 0 da0 register m32c/8a group 19. d/a converter rev.1.00 jul 15, 2007 page 273 of 352 rej09b0385-0100 figure 19.2 dacon register, da0 and da1 registers figure 19.3 d/a converter equivalent circuit d/a control register symbol dacon address 039ch bit symbol rw da0e after reset xxxx xx00b da1e ? (b7-b2) rw rw b7 b6 b5 b4 b1 b2 b3 b0 bit name unimplemented. write 0. read as undefined value. function 0: output disabled 1: output enabled d/a0 output enable bit d/a1 output enable bit ? symbol da0, da1 address 0398h, 039ah after reset undefined d/a register i (i = 0,1) b7 b0 function rw rw output value of d/a conversion setting range 00h to ffh 0: output disabled 1: output enabled da0 r 2r notes: 1. the above applies when the da0 register is set to 2ah. 2. d/a1 has the same circuitry as the avove. 3. when the d/a converter is not used, set the daie bit (i = 0,1) in the dacon register to 0 (output disabled) and the dai register to 00h to stop current from flowing into the r-2r resistor to reduce unnecessary power consumption. 4. vref remains connected even if the vcut bit in the ad0con1 register is set to 0 (vref not connected). r r r r r rr 0 da0e 1 2r 2r 2r 2r 2r 2r 2r 2r lsb 0 1 msb avss vref (4) set in the da0 register m32c/8a group 20. crc calculation rev.1.00 jul 15, 2007 page 274 of 352 rej09b0385-0100 20. crc calculation the crc (cyclic redundancy chec k) calculation detects an error in data blocks. a generator polynomial of crc - ccitt (x 16 + x 12 + x 5 + 1) generates crc code. the crc code is a 16-bit code generated for a given length of the data block in bytes. the crc code is stored in the crcd register every time one-byte data is transferred to the crcin register after a default value is written to the crcd register. crc code generation for one-byte da ta is completed in two bus clock cycles. figure 20.1 shows a block diagram of th e crc circuit. figure 20.2 shows crc- associated registers. figure 20.3 shows an example of the crc calculation. figure 20.1 crc calculation block diagram figure 20.2 crcd register, crcin register crcd register high-order bits of data bus low-order bits of data bus 8 low-order bits 8 high-order bits crc code generation circuit x 16 + x 12 + x 5 + 1 crcin register b15 symbol crcd address 037dh - 037ch after reset undefined b0 function rw after default value is written to the crcd register, the crc code can be read from the crcd register by writing data to the crcin register. bit position of the default value is inverted. the inverted value is read as the crc code. 0000h to ffffh crc data register rw setting range b8 b7 b7 symbol crcin adddress 037eh b0 function rw data input. inverse bit position of data 00h to ffh crc input register rw setting range after reset undefined m32c/8a group 20. crc calculation rev.1.00 jul 15, 2007 page 275 of 352 rej09b0385-0100 figure 20.3 crc calculation crc calculation for m32c crc calculation and se tup procedure to generate crc code for 80c4h crc code: a remainder of division, generator polynomial: x 16 + x 12 + x 5 + 1 (1 0001 0000 0010 0001b) crcd register setting steps (1) invert a bit position of 80c4h per byte by program 80h 01h, c4h 23h (2) set 0000h (default value) crcin register (3) set 01h bit position of the crc code for 80h (9188h) is inverted to 1189h, which is stored into the crcd register in the 3rd cycle. (4) set 23h crcd register crcin register bit position of the crc code for 80c4h (8250h) is inverted to 0a41h, which is stored into the crcd register in the 3rd cycle. crcd register details of crc calculation as shown in (3) above, bit position of 01h (00000001b) written to the crcin register is inverted to 10000000b. add 1000 0000 0000 0000 0000 0000b, as 10000000b plus 16 digits, to 0000h as the default value of the crcd register to perform the modulo-2 division. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 0001 0001 1000 1001b (1189h), the remainder 1001 0001 100 0 1000b (9188h) with inversed bit position, can be read from the crcd register. when going on to (4) above, 23h (00100011b) written in the crcin register is inverted to 11000100b. add 1100 0100 0000 0000 0000 0000b plus 16 digits, to 1001 0001 1000 1000b as a remainder of (3) left in the crcd register to perform the modulo-2 division. 0000 1010 0100 0001b (0a41h), the remainder with in verted bit position, can be read from crcd register. 1189h 0a41h generator polynomial 1000 1000 data 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1001 0001 1000 1000 modulo-2 arithmetic is calculated on the law below 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 1000 1000 0001 0000 1 crc code b15 b0 b0 b0 b0 b0 b15 b15 b7 b7 value of the crcin register with inversed bit position generator polynomial m32c/8a group 21. x/y conversion rev.1.00 jul 15, 2007 page 276 of 352 rej09b0385-0100 21. x/y conversion the x/y conversion rotates a 16 x 16 matrix data by 90 degr ees and also inverts high-order bits and low-order bits of a 16-bit data. figure 21.1 shows the xyc register. the 16-bit xir register (i = 0 to 15) an d 16-bit yjr register (j = 0 to 15) are allocated to the same address. the xir register is a write-only register, whil e the yjr register is a r ead-only register. access re gisters xir and yjr from an even address in 16-bit units. perfor mance cannot be guaranteed if registers xir and yjr are accessed in 8-bit units. figure 21.1 xyc register the xyc0 bit in the xyc register determ ines how to read the yjr register. when setting the xyc0 bit to 0 (data converted) and reading the yjr regist er, all the bits j in registers x0r to x15r can be read. for example, bit 0 in the x0r register can be read when reading bit 0 in the y0r register, bit 0 in the x1r register when reading bit 1 in the y0r register..., bit 0 in the x14r re gister when reading bit 14 in the y0r register, and bit 0 in the x15r register when readi ng bit 15 in the y0r register. figure 21.2 shows a conversion table when the xyc0 bit is set to 0. figure 21.3 shows an example of the x/y conversion. unimplemented. write 0. read as undefined value. read mode set bit x/y control register symbol xyc address 02e0h bit symbol rw xyc0 after reset xxxx xx00b xyc1 ? ( b7-b2) rw rw b7 b6 b5 b4 b1 b2 b3 b0 bit name function 0: data converted 1: data not converted write mode set bit ? 0: bit alignment not converted 1: bit alignment converted m32c/8a group 21. x/y conversion rev.1.00 jul 15, 2007 page 277 of 352 rej09b0385-0100 figure 21.2 conversion table when the xyc0 bit is set to 0 figure 21.3 x/y conversion bits in xir register read address write address bits in yjr register x0r register x1r register x2r register x3r register x4r register x5r register x6r register x7r register x8r register x9r register x10r register x11r register x12r register x13r register x14r register x15r register y 0 r r e g i s t e r y 1 r r e g i s t e r y 2 r r e g i s t e r y 3 r r e g i s t e r y 4 r r e g i s t e r y 5 r r e g i s t e r y 6 r r e g i s t e r y 7 r r e g i s t e r y 8 r r e g i s t e r y 9 r r e g i s t e r y 1 0 r r e g i s t e r y 1 1 r r e g i s t e r y 1 2 r r e g i s t e r y 1 3 r r e g i s t e r y 1 4 r r e g i s t e r y 1 5 r r e g i s t e r b15 b 1 5 b0 b 0 i = 0 to 15 j = 0 to 15 x0r register x1r register x2r register x3r register x4r register x5r register x6r register x7r register x8r register x9r register x10r register x11r register x12r register x13r register x14r register x15r register b15 b0 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b15 b0 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 y 0 r r e g i s t e r y 1 r r e g i s t e r y 2 r r e g i s t e r y 3 r r e g i s t e r y 4 r r e g i s t e r y 5 r r e g i s t e r y 6 r r e g i s t e r y 7 r r e g i s t e r y 8 r r e g i s t e r y 9 r r e g i s t e r y 1 0 r r e g i s t e r y 1 1 r r e g i s t e r y 1 2 r r e g i s t e r y 1 3 r r e g i s t e r y 1 4 r r e g i s t e r y 1 5 r r e g i s t e r m32c/8a group 21. x/y conversion rev.1.00 jul 15, 2007 page 278 of 352 rej09b0385-0100 when setting the xyc0 bit in the xyc register to 1 (dat a not converted) and reading the yjr register, the value written to the xir register can be read. figure 21.4 shows a conversion table when the xyc0 bit is set to 1. figure 21.4 conversion table when the xyc0 bit is set to 1 the xyc1 bit in the xyc register selects bi t alignment written to the xir register. when the xyc1 bit is set to 0 (bit alignm ent not converted) and writing to the xi r register, bit alignment is written as is. when the xyc1 bit is set to 1 (bit alignment converted) and writing to the xir register, inverted bit alignment is written. figure 21.5 shows a conversion when the xyc1 bit is set to 1. figure 21.5 conversion when the xyc1 bit is set to 1 bits in xir register write address read address x0r register, x1r register, x2r register, x3r register, x4r register, x5r register, x6r register, x7r register, x8r register, x9r register, x10r register, x11r register, x12r register, x13r register, x14r register, x15r register, b15 b0 bits in yjr register i = 0 to 15 j = 0 to 15 y 0 r r e g i s t e r y 1 r r e g i s t e r y 2 r r e g i s t e r y 3 r r e g i s t e r y 4 r r e g i s t e r y 5 r r e g i s t e r y 6 r r e g i s t e r y 7 r r e g i s t e r y 8 r r e g i s t e r y 9 r r e g i s t e r y 1 0 r r e g i s t e r y 1 1 r r e g i s t e r y 1 2 r r e g i s t e r y 1 3 r r e g i s t e r y 1 4 r r e g i s t e r y 1 5 r r e g i s t e r write data xir register (i = 0 to 15) b15 b15 b0 b0 m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 279 of 352 rej09b0385-0100 22. programmable i/o ports 75 programmable i/o ports, p6 to p15 (excluding p8_5), are available in the 144-pin package, and 39 programmable i/o ports, p6 to p10 (excluding p8_5), are available in the 100-pin package. in microprocessor mode, p0 to p5 function as bus control pins and cannot be used as i/o ports. p1_0 to p1_7, however, can be used as i/o ports when using with 8-bit external bus width only. the port pi direction registers determine individual port status, input or output. the pull-up control registers determine whether the ports, divided into groups of four, are pulled up or not. p8_5 is an input-only port and cannot be pulled up internally. the p8_5 bit in the p8 register indicates an nmi input level since p8_5 shares its pin with nmi . figures 22.1 to 22.4 show programmable i/o port configurations. each pin functions as a programmable i/o port or i/o pin for internal peripheral functions, or bus control pin. to use as an i/o pin for peripheral functions, refer to the description for individual peripheral functions. refer to 8. bus when used as a bus control pin. registers associated with the prog rammable i/o ports are as follows. 22.1 port pi direction register (pdi register, i = 0 to 15) figure 22.5 shows the pdi register. the pdi register configures a programma ble i/o port as either input or output. each bit in the pdi register corresponds to one port. in microprocessor mode, the pdi register corresponding to the following bus control pins cannot be written: a0 to a22, a23 , d0 to d15, cs0 to cs3 , wrl / wr , wrh / bhe , rd, bclk / ale / clkout, hlda / ale, hold , ale, and rdy . no bit controlling p8_5 is provided in the pdi register. 22.2 port pi register (pi register, i = 0 to 15) figure 22.6 shows the pi register. the mcu inputs/outputs data from/to external devices by r eading and writing to the pi register. the pi register consists of a port latch to hold output data and a circuit to read the pin level. each bit in the pi register corresponds to one port. in microprocessor mode, the pi register corresponding to the following bus control pins cannot be written, nor read the port level: a0 to a22, a23 , d0 to d15, cs0 to cs3 , wrl / wr , wrh / bhe , rd , bclk / ale / clkout, hlda / ale, hold , ale, and rdy . 22.3 function select register a (psj re gister, j = 0 to 3) figures 22.7 to 22.8 show the psj registers. the psj register selects either i/o port or peripheral function output if thes e functions share a single pin (excluding da0 and da1). when multiple peripheral function outputs are assigned to a single pin, set registers psl0 to psl3, and psc to select which function to use. tables 22.2 to 22.6 list peripheral func tion output control settings for each pin. 22.4 function select register b (pslk register, k = 0 to 3) figures 22.9 to 22.10 show the pslk register. when multiple peripheral function outputs are assigned to a single pin, the pslk register select which peripheral function output to use. refer to 22.8 analog input and other peripheral function input for information on bits psl3_3 to psl3_6 in the psl3 register. 22.5 function select regi ster c (psc register) figure 22.11 shows the psc register. when multiple peripheral function outputs are assigned to a single pin, the psc regist er selects which peripheral function output to use. refer to 22.8 analog input and other peripheral function input for information on the psc_7 bit in the psc register. m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 280 of 352 rej09b0385-0100 22.6 pull-up control regi ster 0 to 4 (pur0 to pur4 registers) figures 22.12 to 22.15 show registers pur0 to pur4. registers pur0 to pur4 select whether the ports, divided in to groups of four, are pulled up or not. set the bit in registers pur0 to pur4 to 1 (pull-up) and the bit in th e pdi register to 0 (input mode) to pull-up the corresponding port. in microprocessor mode, set bits, corresponding to the bus control pins (p0 to p5), in registers pur0 and pur1 to 0 (no pull-up). p1 can be pulled up when they are used as input ports in microprocessor mode. 22.7 port control register (pcr register) figure 22.16 shows the pcr register. the pcr register selects either cmos ou tput or n-channel open drain output as port p1 output format. when the pcr0 bit is set to 1, p channel in the cmos port is turned off at all times and in result port p1 becomes n-channel open drain output. this is, however, pseudo open drain. therefore, the absolute maximum rating of the input voltage is from -0.3 v to vcc2 + 0.3 v. to use port p1 as data bus in microprocessor mode, set th e pcr0 bit to 0 (cmos output). when port p1 is used as a port in microprocessor mode, set the output format using the pcr0 bit. 22.8 analog input and other peripheral function input bits psl3_3 to psl3_6 in the psl3 register, and the psc _7 bit in the psc register separate peripheral function inputs from analog input/output. if the analog i/o shares the pin with other peripheral function inputs, a through current may flow to the peripheral function inputs when an intermediate voltage is applied to the pin. to use the analog i/o (da0, da1, anex0, anex1, or an_4 to an_7), set the corresponding bit to 1 (analog i/ o), and disconnect the peripheral function inputs to preven t an intermediate voltage from being applied to the peripheral function inputs. set the corresponding bit to 0 (except analog i/o) when analog i/o is not used. all the peripheral function inputs except the analog i/o are enabled when the corresponding bit is set to 0, and undefined when the bit is set to 1. when the psc_7 bit is set to 1, the ir bit in the kupic register remains unchanged as 0 even if ki0 to ki3 pin input levels are changed. m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 281 of 352 rej09b0385-0100 figure 22.1 programmable i/o ports (1) : available ? : not available (c) peripheral function input (a) hysteresis (b) peripheral function input p0_0 to p0_7 p2_0 to p2_7 ? ? ? ? ? ? ? ? ? option port p5_5, p5_7 p8_3, p8_4 p8_6, p8_7 p3_0 to p3_7 p4_0 to p4_7 p5_0 to p5_2 ? peripheral function input pdi register port latch peripheral function input pull-up select c a programmable i/o ports b data bus ? ? m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 282 of 352 rej09b0385-0100 figure 22.2 programmable i/o ports (2) (a) hysteresis (b) peripheral function input option port p1_5 to p1_7 ? p1_0 to p1_4 ? programmable i/o ports with the port control register pcr0 bit: bit in the pcr register peripheral function input pdi register port latch pull-up select a b data bus pcr0 bit peripheral function input pdi register port latch pull-up select programmable i/o ports with the function select register data bus t dq r reset nmi inv05 inv03 inv02 value written to inv03 bit write signal to inv03 bit registers ps1 and ps2 peripheral function output port p7_2 to p7_5, p8_0, p8_1 : available ? : not available m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 283 of 352 rej09b0385-0100 figure 22.3 programmable i/o ports (3) (note 4) (a) hysteresis (b) peripheral fucntion input pdi register pull-up select programmable i/o ports with the function select register registers ps0 to ps3 (1, 2) e c port latch b : available ? : not available notes: 1. for p5_3, use the pm07 bit in the pm0 register, bits pm 15 and pm14 in the pm1 register, and bits cm01 and cm00 in the cm0 register to select clkout or ale output . 2. for p5_4 and p5_6, use bit s pm15 and pm14 to select ale output. 3. p7_0 and p7_1 are n-c hannel open drain output ports. 4. these ports are provi ded in the 144-pin package only. data bus peripheral function output peripheral function input peripheral function input d analog signal a (c) peripheral fucntion input (d) analog i/f (e) circuit ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? option port p5_3 (1) p5_4, p5_6 (2) p6_0 to p6_7 p7_0, p7_1 (3) p7_6, p7_7 p8_2 p9_0 to p9_2 p9_3 to p9_6 p9_7 p10_0 to p10_3 p10_4 to p10_7 p11_0 to p11_3 p11_4, p12_0 p12_1 to p12_3 p12_4 to p12_7 p13_0 to p13_4 p13_5, p13_6 p13_7 p14_0 to p14_3 p14_4 to p14_6 p15_0 p15_1 to p15_3 p15_4 p15_5 to p15_7 m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 284 of 352 rej09b0385-0100 figure 22.4 programmable i/o ports (4) figure 22.5 pd0 to pd15 registers input-only port (p8_5) data bus nmi b7 b6 b5 b4 b1 b2 b3 symbol pd0 to pd3 pd4 to pd7 pd8 pd9, pd10 pd11 pd12, pd13 pd14 pd15 address 03e2h, 03e3h, 03e6h, 03e7h 03eah, 03ebh, 03c2h, 03c3h 03c6h (4) 03c7h (1) , 03cah 03cbh (3, 4) 03ceh, 03cfh (3) 03d2h (3, 4) 03d3h (3) after reset 00h 00h 00x0 0000b 00h xxx0 0000b 00h x000 0000b 00h b0 function bit symbol bit name rw pdi_5 pdi_7 0: input mode (functi ons as input port) 1: output mode (func tions as output port) port pi_3 direction bit port pi_7 direction bit rw rw rw rw pdi_4 rw pdi_3 0: input mode (functi ons as input port) 1: output mode (func tions as output port) 0: input mode (functi ons as input port) 1: output mode (func tions as output port) port pi_5 direction bit port pi_6 direction bit 0: input mode (functi ons as input port) 1: output mode (func tions as output port) pdi_6 port pi direction register (i = 0 to 15) 0: input mode (functi ons as input port) 1: output mode (func tions as output port) port pi_4 direction bit notes: 1. set the pd9 register immediately after the prc2 bit in the prcr register is set to 1 (write enable). do not generate a n interrupt or a dma or dmacii transfer bet ween these two instructions. 2. in microprocessor mode, the pdi register corresponding to the follo wing bus control pins cannot be written: a0 to a22, a23, d0 to d15, cs0 to cs3, wrl/ wr, wrh/bhe, rd, bclk/ale/clkout, ale, ale, rdy. 3. set registers pd11 to pd15 to ffh in the 100-pin package. 4. nothing is implemented to the pd8_5 bit in the pd 8 register, bits pd11_7 to pd11_5 in the pd11 register, and the p14_7 bit in the pd14 register. write a 0. a read f rom these bits returns undefined value. 0: input mode (functi ons as input port) 1: output mode (func tions as output port) port pi_1 direction bit pdi_1 rw 0: input mode (functi ons as input port) 1: output mode (func tions as output port) port pi_2 direction bit rw pdi_2 0: input mode (functi ons as input port) 1: output mode (func tions as output port) port pi_0 direction bit pdi_0 rw m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 285 of 352 rej09b0385-0100 figure 22.6 p0 to p15 registers b7 b6 b5 b4 b1 b2 b3 symbol p0 to p5 p6 to p10 p11 to p15 address 03e0h, 03e1h, 03e4h, 03e5h, 03e8h, 03e9h 03c0h, 03c1h (3) , 03c4h (4) , 03c5h, 03c8h 03c9h (5) , 03cch, 03cdh, 03d0h (5) , 03d1h after reset undefined undefined undefined b0 function bit symbol bit name rw pi_5 pi_7 port pi_3 bit port pi_7 bit rw rw rw rw pi_4 rw pi_3 port pi_5 bit port pi_6 bit pi_6 port pi register (1, 2) (i = 0 to 15) port pi_4 bit notes: 1. in microprocessor mode, the pi register corresponding to the following bus control pins cannot be written: a0 to a22, a 23, d0 to d15, cs0 to cs3, wrl/ wr, wrh/bhe, rd, bclk/ale/clkout, ale, ale, rdy. 2. ports p11 to p15 are provided in the 144-pin package only. 3. p7_0 and p7_1 are n-channel open drain output ports. the pins are placed into high-i mpedance states when the correspon ding bits to p7_0 and p7_1 are set to 1. 4. the p8_5 bit is a read-only bit. 5. nothing is implemented to bits p11_5 to p11_7 in th e p11 register and the p14_7 bit in t he p14 register. write a 0. a read from these bits returns undefined value. port pi_1 bit pi_1 rw port pi_2 bit rw pi_2 input mode (the pdi_j bit (j = 0 to 7) in the pdi register = 0) read: return the pin level. write: write to the port latch. output mode (the pdi_j bit in the pdi register = 1) read: return the port latch value. write: write to the port latch and the port latch value is output from the pin. 0: "l" level 1: "h" level port pi_0 bit pi_0 rw m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 286 of 352 rej09b0385-0100 figure 22.7 ps0 register, ps1 register b7 b6 b5 b4 b1 b2 b3 symbol ps0 address 03b0h after reset 00h b0 function bit symbol bit name rw ps0_5 ps0_7 port p6_3 output function select bit port p6_7 output function select bit rw rw rw rw ps0_4 rw ps0_3 port p6_5 output function select bit port p6_6 output function select bit ps0_6 function select register a0 port p6_4 output function select bit port p6_1 output function select bit ps0_1 rw port p6_2 output function select bit rw ps0_2 0: i/o port/peripheral function input 1: select by the psl0_0 bit port p6_0 output function select bit ps0_0 rw 0: i/o port/peripheral function input 1: select by the psl0_1 bit 0: i/o port/peripheral function input 1: select by the psl0_2 bit 0: i/o port/peripheral function input 1: select by the psl0_3 bit 0: i/o port/peripheral function input 1: select by the psl0_4 bit 0: i/o port/peripheral function input 1: select by the psl0_5 bit 0: i/o port/peripheral function input 1: select by the psl0_6 bit 0: i/o port/peripheral function input 1: select by the psl0_7 bit b7 b6 b5 b4 b1 b2 b3 symbol ps1 address 03b1h after reset 00h b0 function bit symbol bit name rw ps1_5 ps1_7 port p7_3 output function select bit port p7_7 output function select bit rw rw rw rw ps1_4 rw ps1_3 port p7_5 output function select bit port p7_6 output function select bit ps1_6 function select register a1 port p7_4 output function select bit port p7_1 output function select bit ps1_1 rw port p7_2 output function select bit rw ps1_2 0: i/o port/peripheral function input 1: select by the psl1_0 bit port p7_0 output function select bit ps1_0 rw 0: i/o port/peripheral function input 1: select by the psl1_1 bit 0: i/o port/peripheral function input 1: select by the psl1_2 bit 0: i/o port/peripheral function input 1: select by the psl1_3 bit 0: i/o port/peripheral function input 1: select by the psl1_4 bit 0: i/o port/peripheral function input 1: select by the psl1_5 bit 0: i/o port/peripheral function input 1: select by the psl1_6 bit 0: i/o port/peripheral function input 1: do not set to this value m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 287 of 352 rej09b0385-0100 figure 22.8 ps2 register, ps3 register b7 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol ps2 address 03b4h after reset 00x0 0000b b0 function bit symbol bit name rw ? (b5) rw ? reserved bits ? (b7-b6) function select register a2 port p8_1 output function select bit ps2_1 rw 0: i/o port/peripheral function input 1: select by the psl2_0 bit port p8_0 output function select bit ps2_0 rw 0: i/o port/peripheral function input 1: select by the psl2_1 bit unimplemented. write 0. read as undefined value. set to 0 b7 b6 b5 b4 b1 b2 b3 symbol ps3 address 03b5h after reset 00h b0 function bit symbol bit name rw ps3_5 ps3_7 port p9_3 output function select bit port p9_7 output function select bit rw rw rw rw ps3_4 rw ps3_3 port p9_5 output function select bit port p9_6 output function select bit ps3_6 function select register a3 (1) port p9_4 output function select bit port p9_1 output function select bit ps3_1 rw port p9_2 output function select bit rw ps3_2 0: i/o port/peripheral function input 1: select by the psl3_0 bit port p9_0 output function select bit ps3_0 rw 0: i/o port/peripheral function input 1: select by the psl3_1 bit 0: i/o port/peripheral function input 1: select by the psl3_2 bit 0: i/o port/peripheral function input 1: rts3 0: i/o port/peripheral function input 1: rts4 0: i/o port/peripheral function input 1: clk4 output 0: i/o port/peripheral function input 1: txd4/sda4 output 0: i/o port/peripheral function input 1: select by the psl3_7 bit note: 1. set the ps3 register immediately after the prc2 bit in the prcr register is set to 1 (write enable). do not generate a n interrupt or a dma or dmacii transfer bet ween these two instructions. rw reserved bits ? (b4-b2) set to 0 m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 288 of 352 rej09b0385-0100 figure 22.9 psl0 register, psl1 register b7 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol psl0 address 03b2h after reset 00h b0 function bit symbol bit name rw psl0_5 psl0_7 port p6_3 peripheral function output select bit port p6_7 peripheral function output select bit rw rw rw rw psl0_4 rw psl0_3 port p6_5 peripheral function output select bit port p6_6 peripheral function output select bit psl0_6 function select register b0 port p6_4 peripheral function output select bit port p6_1 peripheral function output select bit psl0_1 rw port p6_2 peripheral function output select bit rw psl0_2 0: rts0 1: do not set to this value port p6_0 peripheral function output select bit psl0_0 rw 0: clk0 output 1: do not set to this value 0: scl0 output 1: stxd0 0: txd0/sda0 output 1: do not set to this value 0: rts1 1: do not set to this value 0: clk1 output 1: do not set to this value 0: scl1 output 1: stxd1 0: txd1/sda1 output 1: do not set to this value b7 0 0 1 b6 b5 b4 b1 b2 b3 symbol psl1 address 03b3h after reset 00h b0 function bit symbol bit name rw psl1_5 ? (b7) port p7_3 peripheral function output select bit reserved bit rw rw rw rw psl1_4 rw psl1_3 port p7_5 peripheral function output select bit port p7_6 peripheral function output select bit psl1_6 function select register b1 port p7_4 peripheral function output select bit port p7_1 peripheral function output select bit psl1_1 rw port p7_2 peripheral function output select bit rw psl1_2 0: select by the psc_0 bit 1: ta0out output port p7_0 peripheral function output select bit psl1_0 rw 0: select by the psc_1 bit 1: stxd2 0: select by the psc_2 bit 1: ta1out output 0: select by the psc_3 bit 1: v 0: select by the psc_4 bit 1: w 0: w 1: do not set to this value 0: do not set to this value 1: ta3out output set to 0 m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 289 of 352 rej09b0385-0100 figure 22.10 psl2 register, psl3 register b7 0 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol psl2 address 03b6h after reset 00x0 0000b b0 function bit symbol bit name rw ? (b5) reserved bits ? rw rw ? (b4-b2) reserved bits ? (b7-b6) function select register b2 port p8_1 peripheral function output select bit psl2_1 rw 0: ta4out output 1: u port p8_0 peripheral function output select bit psl2_0 rw 0: u 1: do not set to this value set to 0 unimplemented. write 0. read as undefined value. set to 0 b7 0 0 b6 b5 b4 b1 b2 b3 symbol psl3 address 03b7h after reset 00h b0 function bit symbol bit name rw psl3_5 psl3_7 port p9_3 peripheral function output select bit (1) port p9_7 peripheral function output select bit rw rw rw rw psl3_4 rw psl3_3 port p9_5 peripheral function output select bit (1) port p9_6 peripheral function output select bit (1) psl3_6 function select register b3 port p9_4 peripheral function output select bit (1) port p9_1 peripheral function output select bit psl3_1 rw port p9_2 peripheral function output select bit rw psl3_2 0: clk3 output 1: do not set to this value port p9_0 peripheral function output select bit psl3_0 rw 0: scl3 output 1: stxd3 0: txd3/sda3 output 1: do not set to this value 0: peripheral function input 1: da0 0: peripheral function input except anex0 1: anex0 0: peripheral function input except anex1 1: anex1 0: scl4 output 1: stxd4 note: 1. if da0, da1, anex0, and anex1 are used with the psl3_ i bit (i = 3 to 6) setting to 0, power consumption may increase. 0: peripheral function input 1: da1 m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 290 of 352 rej09b0385-0100 figure 22.11 psc register b7 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol psc address 03afh after reset 00x0 0000b b0 function bit symbol bit name rw ? (b6-b5) psc_7 port p7_3 peripheral function output select bit port p10_4 to p10_7 peripheral function input select bit rw rw rw psc_4 rw psc_3 reserved bits function select register c port p7_4 peripheral function output select bit port p7_1 peripheral function output select bit psc_1 rw port p7_2 peripheral function output select bit rw psc_2 0: txd2/sda2 output 1: do not set to this value port p7_0 peripheral function output select bit psc_0 rw 0: scl2 output 1: do not set to this value 0: clk2 output 1: v 0: rts2 1: do not set to this value 0: ta2out output 1: do not set to this value set to 0 0: p10_4 to p10_7 or ki0 to ki3 1: an_4 to an_7 (1) note: 1. set bits ilvl2 to ilvl0 in the kupi c register to 000b (interrupt disabled) to change the psc_7 bit. if an_4 to an_7 are used with the psc_7 bit setting to 0, power consumption may increase. m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 291 of 352 rej09b0385-0100 figure 22.12 pur0 register, pur1 register b7 b6 b5 b4 b1 b2 b3 symbol pur0 address 03f0h after reset 00h b0 function bit symbol bit name rw pu05 pu07 p1_4 to p1_7 pull-up p3_4 to p3_7 pull-up rw rw rw rw pu04 rw pu03 p2_4 to p2_7 pull-up p3_0 to p3_3 pull-up pu06 pull-up control register 0 (1) p2_0 to p2_3 pull-up p0_4 to p0_7 pull-up pu01 rw p1_0 to p1_3 pull-up rw pu02 pull-up setting for the corresponding ports 0: not pulled up 1: pulled up p0_0 to p0_3 pull-up pu00 rw b7 b6 b5 b4 b1 b2 b3 symbol pur1 address 03f1h after reset xxxx 0000b b0 function bit symbol bit name rw p5_4 to p5_7 pull-up ? rw ? (b7-b4) pu13 pull-up control register 1 (1) unimplemented. write 0. read as undefined value. p4_4 to p4_7 pull-up pu11 rw p5_0 to p5_3 pull-up rw pu12 pull-up setting for the corresponding ports 0: not pulled up 1: pulled up p4_0 to p4_3 pull-up pu10 rw note: 1. in microprocessor mode, set each bit in the pur0 regist er to 0 since port p0 to p5 are used as bus control pins. when using as i/o ports, it can be selected w hether the ports are pulled up or not. note: 1. in microprocessor mode, set each bit in the pur0 regist er to 0 since port p0 to p5 are used as bus control pins. when using as i/o ports, it can be selected w hether the ports are pulled up or not. m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 292 of 352 rej09b0385-0100 figure 22.13 pur2 register b7 b6 b5 b4 b1 b2 b3 symbol pur2 address 03dah after reset 00h b0 function bit symbol bit name rw pu25 pu27 p7_4 to p7_7 pull-up p9_4 to p9_7 pull-up rw rw rw rw pu24 rw pu23 p8_4 to p8_7 pull-up (2) p9_0 to p9_3 pull-up pu26 pull-up control register 2 p8_0 to p8_3 pull-up p6_4 to p6_7 pull-up pu21 rw p7_2 to p7_3 pull-up (1) rw pu22 pull-up setting for the corresponding ports 0: not pulled up 1: pulled up p6_0 to p6_3 pull-up pu20 rw notes: 1. p7_0 and p7_1 cannot be pulled up. 2. p8_5 cannot be pulled up internally. m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 293 of 352 rej09b0385-0100 figure 22.14 pur3 register b7 b6 b5 b4 b1 b2 b3 symbol pur3 address 03dbh after reset 00h b0 function bit symbol bit name rw pu35 pu37 p11_4 pull-up p13_4 to p13_7 pull-up rw rw rw rw pu34 rw pu33 p12_4 to p12_7 pull-up p13_0 to p13_3 pull-up pu36 pull-up control register 3 p12_0 to p12_3 pull-up p10_4 to p10_7 pull-up pu31 rw p11_0 to p11_3 pull-up rw pu32 pull-up setting for the corresponding ports 0: not pulled up 1: pulled up p10_0 to p10_3 pull-up pu30 rw <144-pin package> b7 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 symbol pur3 address 03dbh after reset 00h b0 function bit symbol bit name rw pull-up control register 3 p10_4 to p10_7 pull-up pu31 rw set to 0 rw ? (b7-b2) pull-up setting for the corresponding ports 0: not pulled up 1: pulled up p10_0 to p10_3 pull-up pu30 rw <100-pin package> reserved bits m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 294 of 352 rej09b0385-0100 figure 22.15 pur4 register b7 b6 b5 b4 b1 b2 b3 symbol pur4 address 03dch after reset xxxx 0000b b0 function bit symbol bit name rw p15_4 to p15_7 pull-up ? rw ? (b7-b4) pu43 pull-up control register 4 (1) unimplemented. write 0. read as undefined value. p14_4 to p14_6 pull-up pu41 rw p15_0 to p15_3 pull-up rw pu42 pull-up setting for the corresponding ports 0: not pulled up 1: pulled up p14_0 to p14_3 pull-up pu40 rw note: 1. set the pur4 register to 00h in the 100-pin package. m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 295 of 352 rej09b0385-0100 figure 22.16 pcr register reserved bits b7 0 0 b6 b5 b4 b1 b2 b3 symbol pcr address 03ffh after reset xxxx x000b b0 function bit symbol bit name rw ? (b7-b3) rw ? port control register 0: cmos output 1: n-channel open drain output (2) port p1 control bit (1) pcr0 rw unimplemented. write 0. read as undefined value. ? (b2-b1) set to 0 notes: 1. in microprocessor mode, set the pcr0 bit to 0 sinc e port p1 is used as data bus . when using port p1 as an i/o port, cmos or n-channel open drain output can be selected. 2. this function is designed to make pseudo open drain by always turning off p channel in the cmos port . therefore, the absolute maximum rating of the input vo ltage is from -0.3 v to vcc + 0.3 v. m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 296 of 352 rej09b0385-0100 table 22.1 unassigned pin handling in microprocessor mode notes: 1. p11 to p15 are provided in the 144-pin package only. 2. when the external clock is applied to the xin pin. figure 22.17 unassigned pin handling pin name handling p1, p6 to p15 (excluding p8_5) (1) set pins to input mode and connect each pin to vss via a resistor (pull-down); or set pins to output mode and leave them open bhe , ale, hlda , xout (2) , bclk leave the pin open hold , rdy connect the pin to vcc2 via a resistor (pull-up) nmi (p8_5) connect the pin to vcc1 via a resistor (pull-up) vref connect the pin to vss mcu p1, p6 to p15 (1) (except for p8_5) (input mode) (output mode) nmi (p8_5) bhe ale avcc avss vref in microprocessor mode open vcc2 open (input mode) ... ... hlda xout bclk hold rdy note: 1. p11 to p15 are provided in the 144-pin package only. vss vcc1 vcc1 m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 297 of 352 rej09b0385-0100 table 22.2 port p6 peripheral function output control table 22.3 port p7 peripheral function output control ps0 register psl0 register bit 0 0: p6_0/cts0 /ss0 1: select by the psl0_0 bit 0: rts0 1: do not set to this value bit 1 0: p6_1/clk0 input 1: select by the psl0_1 bit 0: clk0 output 1: do not set to this value bit 2 0: p6_2/rxd0/scl0 input 1: select by the psl0_2 bit 0: scl0 output 1: stxd0 bit 3 0: p6_3/srxd0/sda0 input 1: select by the psl0_3 bit 0: txd0/sda0 output 1: do not set to this value bit 4 0: p6_4/cts1 /ss1 1: select by the psl0_4 bit 0: rts1 1: do not set to this value bit 5 0: p6_5/ckl1 input 1: select by the psl0_5 bit 0: clk1 output 1: do not set to this value bit 6 0: p6_6/rxd1/scl1 input 1: select by the psl0_6 bit 0: scl1 output 1: stxd1 bit 7 0: p6_7/srxd1/sda1 input 1: select by the psl0_7 bit 0: txd1/sda1 output 1: do not set to this value ps1 register psl1 register psc register bit 0 0: p7_0/ta0out input/ srxd2/sda2 input 1: select by the psl1_0 bit 0: select by the psc_0 bit 1: ta0out output 0: txd2/sda2 output 1: do not set to this value bit 1 0: p7_1/ta0in/tb5in/rxd2/ scl2 input 1: select by the psl1_1 bit 0: select by the psc_1 bit 1: stxd2 0: scl2 output 1: do not set to this value bit 2 0: p7_2/ta1out input/ clk2 input 1: select by the psl1_2 bit 0: select by the psc_2 bit 1: ta1out output 0: clk2 output 1: v bit 3 0: p7_3/ta1in/cts2 /ss2 1: select by the psl1_3 bit 0: select by the psc_3 bit 1: v 0: rts2 1: do not set to this value bit 4 0: p7_4/ta2out input 1: select by the psl1_4 bit 0: select by the psc_4 bit 1: w 0: ta2out output 1: do not set to this value bit 5 0: p7_5/ta2in 1: select by the psl1_5 bit 0: w 1: do not set to this value set to 0 bit 6 0: p7_6/ta3out input 1: select by the psl1_6 bit 0: do not set to this value 1: ta3out output set to 0 bit 7 0: p7_7/ta3in 1: do not set to this value set to 0 ? m32c/8a group 22. programmable i/o ports rev.1.00 jul 15, 2007 page 298 of 352 rej09b0385-0100 table 22.4 port p8 peripheral function output control table 22.5 port p9 peripheral function output control table 22.6 port p10 peripheral function input control ps2 register psl2 register bit 0 0: p8_0/ta4out input 1: select by the psl2_0 bit 0: ta4out output 1: u bit 1 0: p8_1/ta4in 1: select by the psl2_1 bit 0: u 1: do not set to this value bits 2 to 7 set to 000000b ps3 register psl3 register bit 0 0: p9_0/tb0in/clk3 input 1: select by the psl3_0 bit 0: clk3 output 1: do not set to this value bit 1 0: p9_1/tb1in/rxd3/scl3 input 1: select by the psl3_1 bit 0: scl3 output 1: stxd3 bit 2 0: p9_2/tb2in/srxd3/sda3 input 1: select by the psl3_2 bit 0: txd3/sda3 output 1: do not set to this value bit 3 0: p9_3/tb3in/cts3 /ss3 /da0 1: rts3 0: peripheral function input 1: da0 bit 4 0: p9_4/tb4in/cts4 /ss4 /da1 1: rts4 0: peripheral function input 1: da1 bit 5 0: p9_5/anex0/clk4 input 1: clk4 output 0: peripheral function input except anex0 1: anex0 bit 6 0: p9_6/srxd4/anex1/sda4 input 1: txd4/sda4 output 0: peripheral function input except anex1 1: anex1 bit 7 0: p9_7/rxd4 input/adtrg /scl4 input 1: select by the psl3_7 bit 0: scl4 output 1: stxd4 psc register bit 7 0: p10_4 to p10_7 or ki0 to ki3 1: an_4 to an_7 m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 299 of 352 rej09b0385-0100 23. electrical characteristics table 23.1 absolute maximum ratings notes: 1. p11 to p15 are provided in the 144-pin package only. 2. contact a renesas sales office if temperature range of -40 to 85 c is required. symbol parameter condition value unit vcc1, vcc2 supply voltage vcc1 = avcc -0.3 to 6.0 v vcc2 supply voltage ? -0.3 to vcc1 + 0.1 v avcc analog supply voltage vcc1 = avcc -0.3 to 6.0 v vi input voltage reset , cnvss, byte, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) , vref, xin -0.3 to vcc1 + 0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) -0.3 to vcc2 + 0.3 p7_0, p7_1 -0.3 to 6.0 vo output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p14_0 to 14_6, p15_0 to p15_7 (1) , xout -0.3 to vcc1 + 0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) -0.3 to vcc2 + 0.3 p7_0, p7_1 -0.3 to 6.0 pd power dissipation -40 c topr 85 c 500 mw topr operating ambient temperature -20 to 85/ -40 to 85 (2) c tstg storage temperature -65 to 150 c m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 300 of 352 rej09b0385-0100 table 23.2 recommended operating conditions (1) (vcc1 = vcc2 = 3.0 to 5.5 v, topr = -20 to 85 c unless otherwise specified) notes: 1. vih and vil reference for p8_7 apply when p8_7 is used as a programmable input port. it does not apply when p8_7 is used as xcin. 2. p11 to p15 are provided in the 144-pin package only. symbol parameter standard unit min. typ. max. vcc1, vcc2 supply voltage (vcc1 vcc2) 3.0 5.0 5.5 v avcc analog supply voltage vcc1 v vss supply voltage 0 v avss analog supply voltage 0 v vih input high ?h? voltage p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (2) 0.8vcc2 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7 (1) , p9_0 to p9_7, p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (2) , xin, reset , cnvss, byte 0.8vcc1 vcc1 p7_0, p7_1 0.8vcc1 6.0 p0_0 to p0_7, p1_0 to p1_7 (in microprocessor mode) 0.5vcc2 vcc2 vil input low ?l? voltage p2_0 to p2_7,p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (2) 0 0.2vcc2 v p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7 (1) , p9_0 to p9_7, p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (2) , xin, reset , cnvss, byte 0 0.2vcc1 p0_0 to p0_7, p1_0 to p1_7 (in microprocessor mode) 0 0.16vcc2 m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 301 of 352 rej09b0385-0100 table 23.3 recommended operating conditions (2) (vcc1 = vcc2 = 3.0 to 5.5 v, topr = -20 to 85 c unless otherwise specified notes: 1. average output current is the average value within 100 ms. 2. a total iol(peak) of p0, p1, p2, p8_6, p8_7, p9, p10, p11, p14, and p15 must be 80 ma or less. a total iol(peak) of p3, p4, p5, p6, p7,p8_0 to p8_4, p12, and p13 must be 80 ma or less. a total ioh(peak) of p0, p1, p2, and p11 must be -40 ma or less. a total ioh(peak) of p8_6 to p8_7, p9, p10, p14, and p15 must be -40 ma or less. a total ioh(peak) of p3, p4, p5, p12, and p13 must be -40 ma or less. a total ioh(peak) of p6, p7, and p8_0 to p8_4 must be -40 ma or less. 3. p11 to p15 are provided in the 144-pin package only. symbol parameter standard unit min. typ. max. ioh(peak) peak output high ?h? current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) -10.0 ma ioh(avg) average output ?h? current (1) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) -5.0 ma iol(peak) peak output ?l? current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) 10.0 ma iol(avg) average output ?l? current (1) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) 5.0 ma m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 302 of 352 rej09b0385-0100 table 23.4 recommended operating conditions (3) (vcc1 = vcc2 = 3.0 to 5.5 v, topr = -20 to 85 c unless otherwise specified) symbol parameter standard unit min. typ. max. f(cpu) cpu clock frequency (same frequency as f(bclk)) vcc1 = 4.2 to 5.5v 0 32 mhz vcc1 = 3.0 to 5.5v 0 24 mhz f(xin) main clock input frequency vcc1 = 4.2 to 5.5v 0 32 mhz vcc1 = 3.0 to 5.5v 0 24 mhz f(xcin) sub clock frequency 32.768 50 khz f(ring) on-chip oscillator frequency 0.5 1 2 mhz f(vco) vco clock frequency (pll frequency synthesizer) 20 80 mhz f(pll) pll clock frequency vcc1 = 4.2 to 5.5v 10 32 mhz vcc1 = 3.0 to 5.5v 10 24 mhz tsu(pll) wait time to stabilize pll frequency synthesizer vcc1 = 5.0v 5 ms vcc1 = 3.3v 10 ms m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 303 of 352 rej09b0385-0100 table 23.5 electrical characteristics (1) (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 32 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. symbol parameter condition standard unit min. typ. max. voh output high ?h? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) ioh = -5 ma vcc2 - 2.0 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) ioh = -5 ma vcc1 - 2.0 vcc1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7 p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) ioh = -200 a vcc2 - 0.3 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) ioh = -200 a vcc1 - 0.3 vcc1 xout ioh = -1 ma 3.0 vcc1 v xcout high drive capability no load applied 2.5 v low drive capability no load applied 1.6 v vol output low ?l? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) iol = 5 ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) iol = 200 a0.45v xout iol = 1 ma 2.0 v xcout high drive capability no load applied 0v low drive capability no load applied 0v vt+ - vt- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int 5 , adtrg , cts0 to cts 4 , clk0 to clk4, ta0out to ta4out, nmi , ki0 to ki3 , rxd0 to rxd4, scl0 to scl4, sda0 to sda4 0.2 1.0 v reset 0.2 1.8 v vcc1 = vcc2 = 5v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 304 of 352 rej09b0385-0100 table 23.6 electrical characteristics (2) (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 32 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. table 23.7 electrical charac teristics (3) (vcc1 = vcc2 = 5.5 v, vss = 0 v, topr = 25 c ) symbol parameter condition standard unit min. typ. max. iih input high ?h? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 5 v 5.0 a iil input low ?l? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 0v -5.0 a rpullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) vi = 0v 20 40 167 k rfxin feedback resistance xin 1.5 m rfxcin feedback resistance xcin 10 m vram ram data retention voltage in stop mode 2.0 v symbol parameter condition standard unit min. typ. max. icc power supply current romless version f(cpu) = 32 mhz 28 45 ma f(cpu) = 16 mhz 16 ma f(cpu) = 8 mhz 10 ma f(cpu) = f(ring) in on-chip oscillator low-power consumption mode 1ma f(cpu) = 32 khz in low-power consumption mode 25 a f(cpu) = f(ring) after entering wait mode from on-chip oscillator low-power consumption mode 50 a stop mode (while clock is stopped) 0.8 5 a stop mode (while clock is stopped) topr = 85 c50 a vcc1 = vcc2 = 5v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 305 of 352 rej09b0385-0100 table 23.8 a/d conversion characteristics (vcc1 = vcc2 = avcc = vref = 4.2 to 5. 5 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 32mhz unless otherwise specified) notes: 1. the value is obtained when ad frequency is at 16 mhz. keep ad frequency at 16 mhz or less. 2. with using the sample and hold function note: 1. measured when one d/a converter is used, and the dai regist er (i = 0, 1) of the unused d/a converter is set to 00h. the current flown into the resistor ladder in the a/ d converter is excluded. ivref flows even if the vcut bit in the ad0con1 register is set to 0 (vref not connected) symbol parameter measurement condition standard unit min. typ. max. ? resolution vref = vcc1 10 bits inl integral nonlinearity error vref = vcc1 = vcc2 = 5 v an_0 to an_7, an15_0 to an15_7, anex0, anex1 3 lsb external op-amp connection mode 7 lsb dnl differential nonlinearity error 1 lsb ? offset error 3 lsb ? gain error 3 lsb rladder resistor ladder vref = vcc1 8 40 k tconv 10-bit conversion time (1)(2) 2.06 s tconv 8-bit conversion time (1)(2) 1.75 s tsamp sampling time (1) 0.188 s vref reference voltage 2 vcc1 v via analog input voltage 0 vref v table 23.9 d/a conversion characteristics (vcc1 = vcc2 = vref = 4.2 to 5.5 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 32mhz unless otherwise specified) symbol parameter measurement condition standard unit min. typ. max. ? resolution 8bits ? absolute accuracy 1.0 % tsu setup time 3 s ro output resistance 4 10 20 k ivref reference power supply input current (note 1) 1.5 ma vcc1 = vcc2 = 5v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 306 of 352 rej09b0385-0100 table 23.10 voltage detection circ uit electrical characteristics (vcc1 = vcc2 = 3.0 to 5.5 v, vss = 0 v, topr = 25 c unless otherwise specified) notes: 1. vdet4 > vdet3 2. vdet3r > vdet3 is not guaranteed. table 23.11 power supply timing characteristics note: 1. when vcc1= 5 v figure 23.1 power supply timing diagram symbol parameter standard unit min. typ. max. vdet4 vdet4 detection voltage vcc1 = 3.0 v to 5.5 v 3.3 3.8 4.4 v vdet3 vdet3 detection voltage 3.0 v vdet3s hardware reset 2 hold voltage 2.0 v vdet3r hardware reset 2 release voltage 3.1 v symbol parameter measu rement condition standard unit min. typ. max. td(p-r) wait time to stabiliz e internal supply voltage when power-on vcc1 = 3.0 to 5.5 v 2 ms td(s-r) wait time to release hardware reset 2 vcc1 = vdet3r to 5.5 v 6 (1) 20 ms td(e-a) start-up time for vdet3 and vdet4 detection circuit vcc1 = 3.0 to 5.5 v 20 s td(p-r) vcc1 cpu clock recommended operating voltage td(p-r) wait time to stabilize internal supply voltage when power-on td(s-r) vcc1 cpu clock vdet3r td(s-r) wait time to release hardware reset 2 td(e-a) td(e-a) start-up time for vdet3 and vdet4 detection circuit vc26, vc27 vdet3 and vdet4 detection circuit stop operating vcc1 = vcc2 = 5v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 307 of 352 rej09b0385-0100 table 23.12 external clock input i = 0 to 4 i = 0 to 4 i = 0 to 4 i = 0 to 4 symbol parameter standard unit min. max. tc external clock input cycle time 31.25 ns tw(h) external clock input high (?h?) pulse width 13.75 ns tw(l) external clock input low (?l?) pulse width 13.75 ns tr external clock rise time 5 ns tf external clock fall time 5 ns table 23.13 timer a input (count source input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 100 ns tw(tah) taiin input hi gh (?h?) pulse width 40 ns tw(tal) taiin input low (?l?) pulse width 40 ns table 23.14 timer a input (gate signal input in timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 400 ns tw(tah) taiin input high (?h?) pulse width 200 ns tw(tal) taiin input low (?l?) pulse width 200 ns table 23.15 timer a input (external tr igger input in one-shot timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 200 ns tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns table 23.16 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns vcc1 = vcc2 = 5v timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 308 of 352 rej09b0385-0100 timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) i = 0 to 4 i = 0 to 4 i = 0 to 5 i = 0 to 5 i = 0 to 5 table 23.17 timer a input (counter increment/decrement input in event counter mode) symbol parameter standard unit min. max. tc(up) taiout input cycle time 2000 ns tw(uph) taiout input high (?h?) pulse width 1000 ns tw(upl) taiout input low (?l?) pulse width 1000 ns tsu(up-tin) taiout input setup time 400 ns th(tin-up) taiout input hold time 400 ns table 23.18 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 800 ns tsu(tain-taout) taiout input setup time 200 ns tsu(taout-tain) taiin input setup time 200 ns table 23.19 timer b input (count source input in event counter mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time (counted on one edge) 100 ns tw(tbh) tbiin input high (?h?) pulse width (counted on one edge) 40 ns tw(tbl) tbiin input low (?l?) pulse width (counted on one edge) 40 ns tc(tb) tbiin input cycle time (counted on both edges) 200 ns tw(tbh) tbiin input high (?h?) pulse width (counted on both edges) 80 ns tw(tbl) tbiin input low (?l?) pulse width (counted on both edges) 80 ns table 23.20 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns table 23.21 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns vcc1 = vcc2 = 5v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 309 of 352 rej09b0385-0100 timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) i=0 to 4 i=0 to 5 table 23.22 a/d trigger input symbol parameter standard unit min. max. tc(ad) adtrg input cycle time (required for trigger) 1000 ns tw(adl) adtrg input low (?l?) pulse width 125 ns table 23.23 serial interface symbol parameter standard unit min. max. tc(ck) clki input cycle time 200 ns tw(ckh) clki input high (?h?) pulse width 100 ns tw(ckl) clki input low (?l?) pulse width 100 ns td(c-q) txdi output delay time 80 ns th(c-q) txdi output hold time 0 ns tsu(d-c) rxdi input setup time 30 ns th(c-d) rxdi input hold time 90 ns table 23.24 external interrupt inti input (edge sensitive) symbol parameter standard unit min. max. tw(inh) inti input high (?h?) pulse width 250 ns tw(inl) inti input low (?l?) pulse width 250 ns vcc1 = vcc2 = 5v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 310 of 352 rej09b0385-0100 table 23.25 microprocessor mode note: 1. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. insert wait states or lower the operation frequency, f(bclk), if the calculated value is negative. symbol parameter standard unit min. max. tac1(rd-db) data input access time (rd standard) (note 1) ns tac1(ad-db) data input access time (ad standard, cs standard) (note 1) ns tac2(rd-db) data input access time (rd standard, when accessing a space with the multiplexed bus) (note 1) ns tac2(ad-db) data input access time (ad standard, when accessing a space with the multiplexed bus) (note 1) ns tsu(db-bclk) data input setup time 26 ns tsu(rdy-bclk) rdy input setup time 26 ns tsu(hold-bclk) hold input setup time 30 ns th(rd-db) data input hold time 0 ns th(bclk-rdy) rdy input hold time 0 ns th(bclk-hold) hold input hold time 0 ns td(bclk-hlda) hlda output delay time 25 ns 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , m = (b 2) + 1) tac1(rd-db) = 10 9 n f(bclk) - 35 [ns] (if external bus cycle is a + b , n = a + b) tac1(ad-db) = 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , m = (b 2) - 1) tac2(rd-db) = 10 9 p f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , p = {(a + b - 1) 2} + 1) tac2(ad-db) = vcc1 = vcc2 = 5v timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 311 of 352 rej09b0385-0100 switching characteristics (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 23.26 microprocessor mode (when accessing external memory space) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. 3. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.2 18 ns th(bclk-ad) address output hold time (bclk standard) -3 ns th(rd-ad) address output hold time (rd standard) (3) 0 ns th(wr-ad) address output hold time (wr standard) (3) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) -3 ns th(rd-cs) chip-select signal output hold time (rd standard) (3) 0 ns th(wr-cs) chip-select signal output hold time (wr standard) (3) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -5 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time -5 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (3) (note 1) ns tw(wr) wr output width (note 2) ns 10 9 f(bclk) 2 - 10 [ns] th(wr-db) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 n f(bclk) 2 - 15 [ns] (if external bus cycle is a + b , n = (b 2) - 1) tw(wr) = 10 9 m f(bclk) - 20 [ns] (if external bus cycle is a + b , m = b) td(db-wr) = vcc1 = vcc2 = 5v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 312 of 352 rej09b0385-0100 switching characteristics (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 23.27 microprocessor mode (when accessing external memory space with multiplexed bus) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 3. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 4. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 5. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.2 18 ns th(bclk-ad) address output hold time (bclk standard) -3 ns th(rd-ad) address output hold time (rd standard) (5) (note 1) ns th(wr-ad) address output hold time (wr standard) (5) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) -3 ns th(rd-cs) chip-select signal output hold time (rd standard) (5) (note 1) ns th(wr-cs) chip-select signal output hold time (wr standard) (5) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -5 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time -5 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (5) (note 1) ns td(bclk-ale) ale signal output delay time (bclk standard) 18 ns th(bclk-ale) ale signal output hold time (bclk standard) -2 ns td(ad-ale) ale signal output delay time (address standard) (note 3) ns th(ale-ad) ale signal output hold time (address standard) (note 4) ns tdz(rd-ad) address output float start time 8 ns 10 9 f(bclk) 2 - 10 [ns] th(rd-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(rd-cs) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 f(bclk) 2 - 10 [ns] th(wr-db) = 10 9 m f(bclk) 2 - 25 [ns] (if external bus cycle is a + b , m = (b 2) - 1) td(db-wr) = 10 9 n f(bclk) 2 - 20 [ns] (if external bus cycle is a + b , n = a) td(ad-ale) = 10 9 n f(bclk) 2 - 10 [ns] (if external bus cycle is a + b , n = a) th(ale-ad) = vcc1 = vcc2 = 5v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 313 of 352 rej09b0385-0100 figure 23.2 p0 to p15 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30 pf p11 p12 p13 p14 p15 note 1 note: 1. p11 to p15 are provided in the 144-pin package only. m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 314 of 352 rej09b0385-0100 figure 23.3 vcc1 = vcc2 = 5 v timing diagram (1) vcc1=vcc2=5v taiin input tc(ta) tw(tah) tw(tal) taiout input tc(up) tw(uph) tw(upl) taiout input (counter increment/ decrement select input) taiin input (count on falling edge) taiin input (count on rising edge) th(tin-up) tsu(up-tin) in event counter mode tbiin input tc(tb) tw(tbh) tw(tbl) adtrg input tc(ad) tw(adl) clki tc(ck) tw(ckh) tw(ckl) txdi th(c-q) td(c-q) rxdi tsu(d-c) th(c-d) inti input tw(inl) tw(inh) nmi input 2 cpu clock cycles + 300 ns or more 2 cpu clock cycles + 300 ns or more ("l" width) xin input tc tw(l) tw(h) tr tf taiin input taiout input in event counter mode with two-phase pulse tc(ta) tsu(tain-taout) tsu(tain-taout) tsu(taout-tain) tsu(taout-tain) m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 315 of 352 rej09b0385-0100 figure 23.4 vcc1 = vcc2 = 5 v timing diagram (2) microprocessor mode bclk rd (separate bus) wr, wrl, wrh (separate bus) rd (multiplexed bus) wr, wrl, wrh (multiplexed bus) rdy input tsu(rdy-bclk) th(bclk-rdy) hi-z tsu(hold-bclk) td(bclk-hlda) bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 measurement conditions -vcc1 = vcc2 = 4.2 to 5.5 v -input high and low voltage: vih = 4.0 v, vil = 1.0 v -output high and low voltage: voh = 2.5 v, vol = 2.5 v vcc1=vcc2=5v th(bclk-hold) td(bclk-hlda) m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 316 of 352 rej09b0385-0100 figure 23.5 vcc1 = vcc2 = 5 v timing diagram (3) vcc1=vcc2=5v microprocessor mode (when accessing an external memory space) notes: 1. values guaranteed only when the mcu is used stand-alone. a maximum of 35 ns is guaranteed for td(bclk-ad) + tsu(db-bclk). 2. varies with operation frequency: tac1(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) + 1) tac1(ad-db) = (tcyc x n - 35) ns.max (if external bus cycle a + b , n = a + b) read timing (1 + 1 bus cycle) write timing (1 + 1 bus cycle) notes: 3. varies with operation frequency: t d(db-wr) = (tcyc x m - 20) ns.min (if external bus cycle a + b , m = b) t h(wr-db) = (tcyc / 2 - 10) ns.min t h(wr-ad) = (tcyc / 2 - 10) ns.min t h(wr-cs) = (tcyc / 2 - 10) ns.min t w(wr) = (tcyc / 2 x n - 15) ns.min (if external bus cycle a + b , n = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 4.2 to 5.5 v - input high and low voltage: vih = 2.5 v, vil = 0.8 v - output high and low voltage: voh = 2.0 v, vol = 0.8 v tcyc= 10 9 f(bclk) bclk csi adi bhe dbi t h(bclk-cs) -3ns.min t d(bclk-cs) 18ns.max tcyc t d(bclk-ad) 18ns.max t h(wr-ad) (3) t h(bclk-wr) -5ns.min t d(db-wr) (3) th (bclk-ad) -3ns.min t d(bclk-wr) 18ns.max t w(wr) (3) t h(wr-db) (3) t h(wr-cs) (3) wr,wrl,wrh bclk csi adi bhe rd db t h(bclk-cs) -3ns.min t h(rd-cs) 0ns.min t d(bclk-cs) 18ns.max (1) tcyc t d(bclk-ad) 18ns.max (1) 18ns.max t d(bclk-rd) t h(rd-ad) 0ns.min t h(bclk-rd) -5ns.min t ac1(rd-db) (2) t ac1(ad-db) (2) hi-z t h(rd-db) 0ns.min t su(db-bclk) 26ns.min (1) th (bclk-ad) -3ns.min m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 317 of 352 rej09b0385-0100 figure 23.6 vcc1 = vcc2 = 5 v timing diagram (4) bclk csi adi bhe rd ale td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (1) th(ale-ad) (1) tdz(rd-ad) 8ns.max tac2(rd-db) (1) th(bclk-cs) -3ns.min th(rd-db) 0ns.min th(bclk-ad) -3ns.min td(bclk-ad) 18ns.max adi /dbi td(bclk-rd) 18ns.max tac2(ad-db) (1) th(bclk-rd) -5ns.min th(rd-ad) (1) tcyc address notes: 1. varies with operation frequency: t d(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) t h(ale-ad) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b , n = a) t h(rd-ad) = (tcyc / 2 - 10) ns.min, t h(rd-cs) = (tcyc / 2 - 10) ns.min t ac2(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) - 1) t ac2(ad-db) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b , p = {(a + b - 1) x 2} + 1) notes: 1. varies with operation frequency: t d(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) t h(ale-ad) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b , n = a) t h(wr-ad) = (tcyc / 2 - 10) ns.min, t h(wr-cs) = (tcyc / 2 - 10) ns.min t h(wr-db) = (tcyc / 2 - 10) ns.min t d(db-wr) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b , m = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 4.2 to 5.5 v - input high and low voltage vih = 2.5 v, vil = 0.8 v - output high and low voltage voh = 2.0 v, vol = 0.8 v address vcc1=vcc2=5v microprocessor mode (when accessing an external memory space with the multiplexed bus) read timing (2 + 2 bus cycle) tcyc= 10 9 f(bclk) bclk csi adi bhe wr,wrl,wrh write timing (2 + 2 bus cycle) td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (2) th(ale-ad) (2) td(db-wr) (2) th(wr-cs) (2) td(bclk-ad) 18ns.max td(bclk-wr) 18ns.max th(bclk-wr) -5ns.min tcyc address data output th(wr-db) (2) adi /dbi ale address th(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min th(rd-cs) (1) data input tsu(db-bclk) 26ns.min th(wr-ad) (2) m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 318 of 352 rej09b0385-0100 table 23.28 electrical characteristics (1) (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 24 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. symbol parameter condition standard unit min. typ. max. voh output high ?h? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) ioh = -1 ma vcc2 - 0.6 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) vcc1 - 0.6 vcc1 xout ioh = -0.1 ma 2.7 vcc1 v xcout high drive capability no load applied 2.5 v low drive capability no load applied 1.6 v vol output low ?l? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) iol = 1 ma 0.5 v xout iol = 0.1 ma 0.5 v xcout high drive capability no load applied 0v low drive capability no load applied 0v vt+ - vt- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int 5 , adtrg , cts0 to cts 4 , clk0 to clk4, ta0out to ta4out, nmi , ki0 to ki3 , rxd0 to rxd4, scl0 to scl4, sda0 to sda4 0.2 1.0 v reset 0.2 1.8 v vcc1 = vcc2 = 3.3 v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 319 of 352 rej09b0385-0100 table 23.29 electrical characteristics (2) (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 24 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. table 23.30 electrical characte ristics (3) (vcc1 = vcc2 = 3.3 v, vss = 0 v, topr = 25 c) symbol parameter condition standard unit min. typ. max. iih input high ?h? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 3 v 4.0 a iil input low ?l? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 0v -4.0 a rpullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) vi=0v 40 70 500 k rfxin feedback resistance xin 3.0 m rfxcin feedback resistance xcin 20.0 m vram ram data retention voltage in stop mode 2.0 v symbol parameter condition standard unit min. typ. max. icc power supply current romless version f(cpu) = 24 mhz 22 33 ma f(cpu) = 16 mhz 15 ma f(cpu) = 8 mhz 9 ma f(cpu) = f(ring) in on-chip oscillator low-power consumption mode 1ma f(cpu) = 32 khz in low-power consumption mode 25 a f(cpu) = f(ring) after entering wait mode from on-chip oscillator low-power consumption mode 45 a stop mode (while clock is stopped) 0.8 5 a stop mode (while clock is stopped) topr = 85 c50 a vcc1 = vcc2 = 3.3 v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 320 of 352 rej09b0385-0100 table 23.31 a/d conversion characteristics (vcc1 = vcc2 = avcc = vref = 3.0 to 3. 6 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 24mhz unless otherwise specified) notes: 1. the value when ad frequency is at 10 mhz. keep ad frequency at 10 mhz or less. if f(cpu) (=fad) is 24 mhz, divide f(cpu) by 3 to make it 8 mhz. the conversion time in this case is 6.1 s. 2. s&h not available. note: 1. measurement when one d/a converter is used, and the dai r egister (i = 0, 1) of the unused d/a converter is set to 00h. the current flown into the resistor ladder in th e a/d converter is excluded. ivref flows even if vcut bit in the ad0con1 register is set to 0 (vref not connected) symbol parameter measurement condition standard unit min. typ. max. ? resolution vref = vcc1 10 bits inl integral nonlinearity error (8-bit) vref = vcc1 = vcc2 = 3.3 v 2 lsb dnl differential nonlinearity error (8-bit) 1 lsb ? offset error (8-bit) 2 lsb ? gain error (8-bit) 2 lsb rladder resistor ladder vref = vcc1 8 40 k tconv 8-bit conversion time (1)(2) 4.9 s vref reference voltage 3 vcc1 v via analog input voltage 0 vref v table 23.32 d/a conversion characteristics (vcc1 = vcc2 = vref = 3.0 to 3.6 v, vss = avss = 0 v at topr = -20 to 85 c, f(cpu) = 24mhz unless otherwise specified) symbol parameter measurement condition standard unit min. typ. max. ? resolution 8bits ? absolute accuracy 1.0 % tsu setup time 3 s ro output resistance 4 10 20 k ivref reference power supply input current (note 1) 1.0 ma vcc1 = vcc2 = 3.3 v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 321 of 352 rej09b0385-0100 timing requirements ( vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified ) i = 0 to 4 i = 0 to 4 i = 0 to 4 i = 0 to 4 table 23.33 external clock input symbol parameter standard unit min. max. tc external clock input cycle time 41 ns tw(h) external clock input high (?h?) pulse width 18 ns tw(l) external clock input low (?l?) pulse width 18 ns tr external clock rise time 5 ns tf external clock fall time 5 ns table 23.34 timer a input (count source input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 100 ns tw(tah) taiin input hi gh (?h?) pulse width 40 ns tw(tal) taiin input low (?l?) pulse width 40 ns table 23.35 timer a input (gate signal input in timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 400 ns tw(tah) taiin input high (?h?) pulse width 200 ns tw(tal) taiin input low (?l?) pulse width 200 ns table 23.36 timer a input (external tr igger input in one-shot timer mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 200 ns tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns table 23.37 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns vcc1 = vcc2 = 3.3 v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 322 of 352 rej09b0385-0100 timing requirements ( vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified ) i = 0 to 4 i = 0 to 4 i = 0 to 5 i = 0 to 5 i = 0 to 5 table 23.38 timer a input (counter increment/decrement input in event counter mode) symbol parameter standard unit min. max. tc(up) taiout input cycle time 2000 ns tw(uph) taiout input high (?h?) pulse width 1000 ns tw(upl) taiout input low (?l?) pulse width 1000 ns tsu(up-tin) taiout input setup time 400 ns th(tin-up) taiout input hold time 400 ns table 23.39 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. tc(ta) taiin input cycle time 2 s tsu(tain-taout) taiout input setup time 500 ns tsu(taout-tain) taiin input setup time 500 ns table 23.40 timer b input (count source input in event counter mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time (counted on one edge) 100 ns tw(tbh) tbiin input high (?h?) pulse width (counted on one edge) 40 ns tw(tbl) tbiin input low (?l?) pulse width (counted on one edge) 40 ns tc(tb) tbiin input cycle time (counted on both edges) 200 ns tw(tbh) tbiin input high (?h?) pulse width (counted on both edges) 80 ns tw(tbl) tbiin input low (?l?) pulse width (counted on both edges) 80 ns table 23.41 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns table 23.42 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns vcc1 = vcc2 = 3.3 v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 323 of 352 rej09b0385-0100 timing requirements (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) i=0 to 4 i=0 to 5 table 23.43 a/d trigger input symbol parameter standard unit min. max. tc(ad) adtrg input cycle time (required for trigger) 1000 ns tw(adl) adtrg input low (?l?) pulse width 125 ns table 23.44 serial interface symbol parameter standard unit min. max. tc(ck) clki input cycle time 200 ns tw(ckh) clki input high (?h?) pulse width 100 ns tw(ckl) clki input low (?l?) pulse width 100 ns td(c-q) txdi output delay time 80 ns th(c-q) txdi output hold time 0 ns tsu(d-c) rxdi input setup time 30 ns th(c-d) rxdi input hold time 90 ns table 23.45 external interrupt inti input (edge sensitive) symbol parameter standard unit min. max. tw(inh) inti input high (?h?) pulse width 250 ns tw(inl) inti input low (?l?) pulse width 250 ns vcc1 = vcc2 = 3.3 v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 324 of 352 rej09b0385-0100 table 23.46 microprocessor mode note: 1. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. insert wait states or lower the operation frequency, f(bclk), if the calculated value is negative. symbol parameter standard unit min. max. tac1(rd-db) data input access time (rd standard) (note 1) ns tac1(ad-db) data input access time (ad standard, cs standard) (note 1) ns tac2(rd-db) data input access time (rd standard, when accessing a space with the multiplexed bus) (note 1) ns tac2(ad-db) data input access time (ad standard, when accessing a space with the multiplexed bus) (note 1) ns tsu(db-bclk) data input setup time 30 ns tsu(rdy-bclk) rdy input setup time 40 ns tsu(hold-bclk) hold input setup time 60 ns th(rd-db) data input hold time 0 ns th(bclk-rdy) rdy input hold time 0 ns th(bclk-hold) hold input hold time 0 ns td(bclk-hlda) hlda output delay time 25 ns 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , m = (b 2) + 1) tac1(rd-db) = 10 9 n f(bclk) - 35 [ns] (if external bus cycle is a + b , n = a + b) tac1(ad-db) = 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , m = (b 2) - 1) tac2(rd-db) = 10 9 p f(bclk) 2 - 35 [ns] (if external bus cycle is a + b , p = {(a + b - 1) 2} + 1) tac2(ad-db) = vcc1 = vcc2 = 3.3 v timing requirements (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 325 of 352 rej09b0385-0100 switching characteristics (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 23.47 microprocessor mode (when accessing external memory space) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. 3. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.2 18 ns th(bclk-ad) address output hold time (bclk standard) 0 ns th(rd-ad) address output hold time (rd standard) (3) 0 ns th(wr-ad) address output hold time (wr standard) (3) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) 0 ns th(rd-cs) chip-select signal output hold time (rd standard) (3) 0 ns th(wr-cs) chip-select signal output hold time (wr standard) (3) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -3 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time 0 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (3) (note 1) ns tw(wr) wr output width (note 2) ns 10 9 f(bclk) 2 - 20 [ns] th(wr-db) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 n f(bclk) 2 - 15 [ns] (if external bus cycle is a + b , n = (b 2) - 1) tw(wr) = 10 9 m f(bclk) - 20 [ns] (if external bus cycle is a + b , m = b) td(db-wr) = vcc1 = vcc2 = 3.3 v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 326 of 352 rej09b0385-0100 switching characteristics (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 23.48 microprocessor mode (when accessing external memory space with multiplexed bus) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 3. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 4. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 5. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 23.2 18 ns th(bclk-ad) address output hold time (bclk standard) 0 ns th(rd-ad) address output hold time (rd standard) (5) (note 1) ns th(wr-ad) address output hold time (wr standard) (5) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) 0 ns th(rd-cs) chip-select signal output hold time (rd standard) (5) (note 1) ns th(wr-cs) chip-select signal output hold time (wr standard) (5) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -3 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time 0 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (5) (note 1) ns td(bclk-ale) ale signal output delay time (bclk standard) 18 ns th(bclk-ale) ale signal output hold time (bclk standard) -2 ns td(ad-ale) ale signal output delay time (address standard) (note 3) ns th(ale-ad) ale signal output hold time (address standard) (note 4) ns tdz(rd-ad) address output float start time 8 ns 10 9 f(bclk) 2 - 10 [ns] th(rd-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(rd-cs) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 f(bclk) 2 - 20 [ns] th(wr-db) = 10 9 m f(bclk) 2 - 25 [ns] (if external bus cycle is a + b , m = (b 2) - 1) td(db-wr) = 10 9 n f(bclk) 2 - 20 [ns] (if external bus cycle is a + b , n = a) td(ad-ale) = 10 9 n f(bclk) 2 - 10 [ns] (if external bus cycle is a + b , n = a) th(ale-ad) = vcc1 = vcc2 = 3.3 v m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 327 of 352 rej09b0385-0100 figure 23.7 vcc1 = vcc2 = 3.3 v timing diagram (1) vcc1=vcc2=3.3v taiin input tc(ta) tw(tah) tw(tal) taiout input tc(up) tw(uph) tw(upl) taiout input (counter increment/ decrement select input) taiin input (count on falling edge) taiin input (count on rising edge) th(tin-up) tsu(up-tin) in event counter mode tbiin input tc(tb) tw(tbh) tw(tbl) adtrg input tc(ad) tw(adl) clki tc(ck) tw(ckh) tw(ckl) txdi th(c-q) td(c-q) rxdi tsu(d-c) th(c-d) inti input tw(inl) tw(inh) nmi input 2 cpu clock cycles + 300 ns or more 2 cpu clock cycles + 300 ns or more ("l" width) xin input tc tw(l) tw(h) tr tf taiin input taiout input in event counter mode with two-phase pulse tc(ta) tsu(tain-taout) tsu(tain-taout) tsu(taout-tain) tsu(taout-tain) m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 328 of 352 rej09b0385-0100 figure 23.8 vcc1 = vcc2 = 3.3 v timing diagram (2) microprocessor mode bclk rd (separate bus) wr, wrl, wrh (separate bus) rd (multiplexed bus) wr, wrl, wrh (multiplexed bus) rdy input tsu(rdy-bclk) th(bclk-rdy) hi-z tsu(hold-bclk) td(bclk-hlda) bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 measurement conditions -vcc1 = vcc2 = 3.0 to 3.6 v -input high and low voltage: vih = 2.4 v, vil = 0.6 v -output high and low voltage: voh = 1.5 v, vol = 1.5 v vcc1=vcc2=3.3v th(bclk-hold) td(bclk-hlda) m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 329 of 352 rej09b0385-0100 figure 23.9 vcc1 = vcc2 = 3.3 v timing diagram (3) vcc1=vcc2=3.3v microprocessor mode (when accessing an external memory space) notes: 1. values guaranteed only when the mcu is used stand-alone. a maximum of 35 ns is guaranteed for td(bclk-ad) + tsu(db-bclk). 2. varies with operation frequency: tac1(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) + 1) tac1(ad-db) = (tcyc x n - 35) ns.max (if external bus cycle a + b , n = a + b) read timing (1 + 1 bus cycle) write timing (1 + 1 bus cycle) notes: 3. varies with operation frequency: t d(db-wr) = (tcyc x m - 20) ns.min (if external bus cycle a + b , m = b) t h(wr-db) = (tcyc / 2 - 20) ns.min t h(wr-ad) = (tcyc / 2 - 10) ns.min t h(wr-cs) = (tcyc / 2 - 10) ns.min t w(wr) = (tcyc / 2 x n - 15) ns.min (if external bus cycle a + b , n = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 3.0 to 3.6 v - input high and low voltage: vih = 1.5 v, vil = 0.5 v - output high and low voltage: voh = 1.5 v, vol = 1.5 v tcyc= 10 9 f(bclk) bclk csi adi bhe dbi t h(bclk-cs) 0ns.min t d(bclk-cs) 18ns.max tcyc t d(bclk-ad) 18ns.max t h(wr-ad) (3) t h(bclk-wr) 0ns.min t d(db-wr) (3) th (bclk-ad) 0ns.min t d(bclk-wr) 18ns.max t w(wr) (3) t h(wr-db) (3) t h(wr-cs) (3) wr,wrl,wrh bclk csi adi bhe rd db t h(bclk-cs) 0ns.min t h(rd-cs) 0ns.min t d(bclk-cs) 18ns.max (1) tcyc t d(bclk-ad) 18ns.max (1) 18ns.max t d(bclk-rd) t h(rd-ad) 0ns.min t h(bclk-rd) -3ns.min t ac1(rd-db) (2) t ac1(ad-db) (2) hi-z t h(rd-db) 0ns.min t su(db-bclk) 30ns.min (1) th (bclk-ad) 0ns.min m32c/8a group 23. electrical characteristics rev.1.00 jul 15, 2007 page 330 of 352 rej09b0385-0100 figure 23.10 vcc1 = vcc2 = 3.3 v timing diagram (4) bclk csi adi bhe rd ale td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (1) th(ale-ad) (1) tdz(rd-ad) 8ns.max tac2(rd-db) (1) th(bclk-cs) 0ns.min th(rd-db) 0ns.min th(bclk-ad) 0ns.min td(bclk-ad) 18ns.max adi /dbi td(bclk-rd) 18ns.max tac2(ad-db) (1) th(bclk-rd) -3ns.min th(rd-ad) (1) tcyc address notes: 1. varies with operation frequency: t d(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) t h(ale-ad) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b , n = a) t h(rd-ad) = (tcyc / 2 - 10) ns.min, t h(rd-cs) = (tcyc / 2 - 10) ns.min t ac2(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) - 1) t ac2(ad-db) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b , p = {(a + b - 1) x 2} + 1) notes: 1. varies with operation frequency: t d(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) t h(ale-ad) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a + b , n = a) t h(wr-ad) = (tcyc / 2 - 10) ns.min, t h(wr-cs) = (tcyc / 2 - 10) ns.min t h(wr-db) = (tcyc / 2 - 20) ns.min t d(db-wr) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b , m = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 3.0 to 3.6 v - input high and low voltage vih = 1.5 v, vil = 0.5 v - output high and low voltage voh = 1.5 v, vol = 1.5 v address vcc1=vcc2=3.3v microprocessor mode (when accessing an external memory space with the multiplexed bus) read timing (2 + 2 bus cycle) tcyc= 10 9 f(bclk) bclk csi adi bhe wr,wrl,wrh write timing (2 + 2 bus cycle) td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (2) th(ale-ad) (2) td(db-wr) (2) th(wr-cs) (2) td(bclk-ad) 18ns.max td(bclk-wr) 18ns.max th(bclk-wr) 0ns.min tcyc address data output th(wr-db) (2) adi /dbi ale address th(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min th(rd-cs) (1) data input tsu(db-bclk) 30ns.min th(wr-ad) (2) m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 331 of 352 rej09b0385-0100 24. usage notes 24.1 power supply 24.1.1 power-on at power-on, supply voltage applied to the vcc1 must meet the svcc standard. (technical update: tn-m16c-116-0311) figure 24.1 svcc timing table 24.1 supply voltage power-up slope symbol parameter standard unit min. typ. max. svcc supply voltage power-up slope (supply voltage range: 0 v to 2.0 v) 0.05 v/ms 0 v svcc supply voltage power-up slope (vcc1) time svcc voltage 2.0 v m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 332 of 352 rej09b0385-0100 24.1.2 power supply ripple stabilize supply voltage to meet the power supply standard listed in table 24.2. table 24.2 power supply ripple figure 24.2 power supply fluctuation timing 24.1.3 noise use thick and shortest possible wiri ng to connect a byp ass capacitor (0.1 f or more) between vcc and vss. symbol parameter standard unit min. typ. max. f(ripple) power supply ripple tolerable frequency (vcc1) (vcc1 = 5 v) 10 khz (vcc1 = 3.3 v) 100 hz vp-p(ripple) power supply ripple voltage fluctuation range (vcc1 = 5 v) 0.5 v (vcc1 = 3.3 v) 0.2 v vcc(| v/ t|) power supply ripple voltage fluctuation rate (vcc1 = 5 v) 1 v/ms (vcc1 = 3.3 v) 0.1 v/ms vp-p(ripple) f(ripple) vcc1 f(ripple) power supply ripple tolerable frequency (vcc1) vp-p(ripple) power supply ripple voltage fluctuation range m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 333 of 352 rej09b0385-0100 24.2 special function registers (sfrs) 24.2.1 100 pin-package set addresses 03cbh, 03ceh, 03cfh, 03d2h, and 03d3h to ffh after reset when using the 100-pin package. address 03dch must be set to 00h after reset. 24.2.2 register settings table 24.3 lists registers containing write-only bits. read-modify-write instructions cannot be used to set these registers. if these registers are se t using a read-modify-write instruction, undefined values are read from the write-only bits in the register and wr itten back to these bits. table 24.4 lists read-modify-write instructions. when establishing new values by modifying previous one s, write the previous values into ram as well as to the register. change the contents of the ram and then transfer the new values to the register. table 24.3 registers with write-only bits note: 1. in one-shot timer mode and pulse width modulation mode only. table 24.4 read-modify-write instructions register address register address wdts register 000eh u3tb register 032bh to 032ah u1brg register 02e9h u2brg register 0339h u1tb register 02ebh to 02eah u2tb register 033bh to 033ah u4brg register 02f9h udf register 0344h u4tb register 02fbh to 02fah ta0 register (1) 0347h to 0346h ta11 register 0303h, 0302h ta1 register (1) 0349h to 0348h ta21 register 0305h, 0304h ta2 register (1) 034bh to 034ah ta41 register 0307h, 0306h ta3 register (1) 034dh to 034ch dtt register 030ch ta4 register (1) 034fh to 034eh ictb2 register 030dh u0brg register 0369h u3brg register 0329h u0tb register 036bh to 036ah function mnemonic transfer movdir bit manipulation bclr, bmcnd, bnot, bset, btstc, btsts shift rolc, rorc, rot, sh a, shanc, shl, shlnc arithmetic abs, adc, adcf, add, addx, dadc , dadd, dec, dsbb, dsub, exts, extz, inc, mul, mulex, mulu, neg, sbb, sub, subx logical and, not, or, xor jump adjnz, sbjnz m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 334 of 352 rej09b0385-0100 24.3 clock generation circuits 24.3.1 main clock ? when the cpu operating frequency is required 24 mhz or more, make an oscillator connected to the main clock circuit (xin-xout), or an exte rnal clock applied to the xin pin have 24 mhz or less frequency, and then multiply the main clock with the pll frequency synthesizer. by using this procedure, a better emc (electromagnetic compatibility) perfo rmance can be achieved than usin g a more than 24 mhz oscillator (external clock). ? if the main clock is selected as the cpu clock while an external clock is applied to the xin pin, do not stop the external clock. (technical update: tn-m16c-109-0309) ? when an external clock is used for the cpu clock, do not set the cm05 bit in the cm0 register to 1 (stopped). 24.3.2 sub clock 24.3.2.1 to oscillate sub clock to oscillate the sub clock, set the cm07 bit in the cm0 register to 0 (clock other than the sub clock) and the cm03 bit to 1 (xcin-xout drive capability high). then, set the cm04 bit in the cm0 register to 1 (xcin- xcout oscillation function). once the sub clock be comes stabilized, set the cm03 bit to 0 (xcin-xout drive capability low). after the above procedure, the sub clock can be used as the cpu clock, or the count source for timer a and timer b. (technical update: tn-16c-119a/ea) 24.3.2.2 oscillation parameter matching if an oscillation circuit constant matching for the sub cl ock oscillation circuit has only been evaluated with the drive capability high, the constant matching fo r drive capability low mu st also be evaluated. contact your oscillator manufacturer for details on the oscillation circuit constant matching. 24.3.3 clock dividing ratio to change bits mcd4 to mcd0, set the pm12 bit in the pm1 register to 0 (no wait state). 24.3.4 power consumption control stabilize the main clock, sub clock, or pll clock prior to switching the clock source for the cpu clock to one of these clocks. 24.3.4.1 wait mode ? when entering wait mode with setting the cm02 bit in the cm0 register to 1 (peripheral clocks stop in wait mode), set bits mcd4 to mcd0 in the mcd register to be the 10-mhz or less cpu clock frequency after dividing the main clock. ? when entering wait mode, the instru ctions following the wait instructi on are stored into the instruction queue, and the program stops. insert at least 4 nop instructions after the wait instruction. ? to enter wait mode, execute the wait instruction while a high-level (?h?) signal is applied to the nmi pin. m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 335 of 352 rej09b0385-0100 24.3.4.2 stop mode ? the mcu cannot enter stop mode if a low-level (?l?) signal is applied to the nmi pin. apply an ?h? signal to enter stop mode. ? to exit stop mode by reset, apply an ?l? signal to reset pin until a main clock oscillation stabilizes. ? if using the nmi interrupt to exit stop mode, use the following procedure to set the cm10 bit in the cm1 register to 1 (all clocks stopped). (technical update: tn-16c-127a/ea) (1) exit stop mode using the nmi interrupt. (2) generate a dummy interrupt. (3) set the cm10 bit to 1 (all clocks stopped). e.g., int #63 ; dummy interrupt bset cm1 ; all clocks stopped /*dummy interrupt routine*/ dummy reit ? when entering stop mode, the instructions following cm10 = 1 instruction are stored into the instruction queue, and the program stops. when stop mode is ex ited, the instruction lined in the queue is executed before the exit interrupt routine is handled. insert a jmp.b instruction as follows after the instruction to set the cm10 bit is set to 1. (technical update: tn-16c-124a/ea) fset i ; i flag is set to 1 bset 0, cm1 ; all clocks stopped (stop mode) jmp.b label_001 ; jmp.b instruction executed (no instruction between jmp.b and label.) label_001: nop ; nop(1) nop ; nop(2) nop ; nop(3) nop ; nop(4) mov.b #0, prcr ; protection set . . . m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 336 of 352 rej09b0385-0100 24.3.4.3 suggestions to reduce power consumption the followings are suggestions to reduce power consumption when programming or designing systems. ports: ? through current may flow into floating input pins. set unassigned pins to input mode and connect them to vss via a resistor (pull down), or set unassigned pins to output mode and leave them open. a/d converter: ? when the a/d conversion is not pe rformed, set the vcut bit in the ad0con1 register to 0 (vref not connected). when the a/d conversion is pe rformed, set the vcut bit to 1 (vref connection) and wait 1 s or longer to start the a/d conversion. d/a converter: ? when the d/a conversion is not performed, set the daie bit (i = 0, 1) in the dacon register to 0 (output disabled) and the dai register to 00h. peripheral function clock stop: ? when entering wait mode from main clock mode, on-c hip oscillator mode, or on-ch ip oscillator low-power consumption mode, power consumption can be reduced by setting the cm02 bit in the cm0 register to 1 to stop peripheral function clock source (fpfc). however, fc32 does not stop by setting the cm02 bit to 1. ? in low-speed mode, do not set the cm02 bit to 1 (peripheral clock stops in wait mode) when entering wait mode. (technical update: tn-m16c-69-0104) m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 337 of 352 rej09b0385-0100 24.4 protection the prc2 bit in the prcr register become s 0 (write disable) by a write to th e sfr area after the prc2 bit is set to 1 (write enable). set a register prot ected by the prc2 bit imme diately after the prc2 bit is set to 1. do not generate an interrupt or a dma or dmacii transfer between these two instructions. m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 338 of 352 rej09b0385-0100 24.5 interrupts 24.5.1 isp setting after reset, isp is initialized to 000000h. the program crash may occur if an interrupt is acknowledged before setting a value to isp. therefore, isp must be set befo re any interrupt request is acknowledged. setting isp to an even address allows interrupt sequences to be executed at a higher speed. to use the nmi interrupt, set isp at the very beginning of the program. the nmi interrupt can be acknowledged after the first instruction has been executed after reset. 24.5.2 nmi interrupt ? the nmi interrupt cannot be disabled. connect the nmi pin to vcc1 via a resistor (pull-up) when not in use. ? the p8_5 bit in the p8 register indicates the voltage level applied to the nmi pin. read the p8_5 bit only to determine the pin level after the nmi interrupt occurs. 24.5.3 int interrupt ? edge sensitive each of ?h? or ?l? width of signals applied to pins int0 to int 5 must be 250 ns or more regardless of the cpu clock frequency. ? level sensitive each of ?h? or ?l? width of signals applied to pins int0 to int 5 must be one cpu clock cycle + 200 ns or more. for example, each of ?h? or ?l? width must be 234 ns or more if the cpu clock is 30 mhz. ? the ir bit in the intiic register (i = 0 to 5) may beco me 1 (interrupt requested) wh en the polarity settings of pins int0 to int5 are changed. set the ir bit to 0 (interrupt no t requested) after the pol arity setting is changed. figure 24.3 shows an exampl e of the switching procedure for an inti interrupt source (i = 0 to 5). m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 339 of 352 rej09b0385-0100 figure 24.3 switching procedure for inti (i = 0 to 5) interrupt source start intiic register: pol bit lvs bit = 0 ifsr register: ifsri bit intiic register: bits ilvl2 to ilvl0 = 000b interrupt disabled select polarity (set to 0 when both edges are selected) select edge sensitive select either one edge or both edge intiic register: ir bit = 0 clear the interrupt request bit end < procedure for edge sensitive > < procedure for level sensitive > i = 0 to 5 start intiic register: pol bit lvs bit = 1 ifsr register: ifsri bit = 0 intiic register: bits ilvl2 to ilvl0 = 000b interrupt disabled select polarity select level sensitive select one edge end intiic register: bits ilvl2 to ilvl0 interrupt enabled intiic register: ir bit = 0 clear the interrupt request bit intiic register: bits ilvl2 to ilvl0 interrupt enabled m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 340 of 352 rej09b0385-0100 24.5.4 changing interr upt contro l register to change the interrupt control register while an interr upt request is disabled, use the following instructions. changing ir bit: the ir bit may not be changed to 0 (interrupt not requested) by writing, depending on which instruction is used. if this causes a problem, use mov instruction to ch ange the register. (technical update: tn-m16c-85-0204) changing any bits other than ir bit: if an interrupt request is generated while writing to the corresponding interrupt control register with instructions such as mov, the ir bit may not become 1 (interrupt requested) and the interrupt is not acknowledged. if this causes a problem, use the following instructions to write to the register: and, or, bclr, bset 24.5.5 changing rlvl register the dmaii bit in the rlvl register is undefined after reset. to use interru pt priority level 7 for an interrupt, set it to 0 before setting the interrupt control register. m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 341 of 352 rej09b0385-0100 24.6 dmac ? set the dmac-associated registers while bits mdi1 and mdi0 (i = 0 to 3) in the channel i are set to 00b (dma disabled). then, set bits mdi1 and mdi0 to 01b (single tr ansfer) or 11b (repeat transf er) at the end of the setup procedure, which enables the dma request of the channel i to be acknowledged. ? write a 1 (requested) to the drq bit when setting the dmisl register. in the m32c/80 series, if a dma request is generated but a receiving channel is not ready (1) , a dma transfer does not occur and the drq bit becomes 0. note: 1. bits mdi1 and mdi0 are set to 00b or the dcti register is 0000h (transferred 0 time). ? to start a dma transfer using a software trigger, set bits dsr and drq in the dmisl register to 1 simultaneously. e.g., or.b #0a0h, dmisl ; set bits dsr and drq to 1 simultaneously ? while the dcti register in the channel i is set to 1, do not generate a dma request in the channel i in the timing that bits mdi1 and mdi0 in the dmdj register (j = 0, 1) corresponding to the channel i are set to 01b (single transfer) or 11b (repeat transfer). (technical update: tn-m16c-88-0209) ? select a peripheral function used as a dma request source after setting the dma-associ ated registers. when the int interrupt is selected as a dma request so urce, do not set the dcti register to 1. ? wait six cpu clock cycles or more by program to enable dma after setting the dmisl register (2) . note: 2. to enable dma means changing bits mdi1 and mdi0 in the dmdj register from 00b (dma disabled) to 01b (single tr ansfer) or 11b (repeat transfer). m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 342 of 352 rej09b0385-0100 24.7 timers 24.7.1 timer a, timer b timers are stopped after reset. set the tais (i = 0 to 4) or tbjs (j = 0 to 5) bit in the tabsr or tbsr register to 1 (count starts) after setting timer ope rating mode, count source, and counter value. the following registers and bits must be changed while the tais or tbjs bit is set to 0 (count stops). ? registers taimr and tbjmr ? udf register ? bits tazie, ta0tgl, and ta0tgh in the onsf register ? trgsr register 24.7.2 timer a 24.7.2.1 timer a (timer mode) ? the tais bit (i = 0 to 4) in the tabsr register is set to 0 (count stops) after reset. set the tais bit to 1 (count starts) after selecting timer operating mode and setting the tai register. ? the tai register indicates a counter value while coun ting at any given time. however, ffffh can be read in the reload timing. a setting value can be read between when the tai register is set while a counter stops and when a counter is started. 24.7.2.2 timer a (event counter mode) ? the tais bit (i = 0 to 4) is set to 0 (count stops) af ter reset. set the tais bit to 1 (count starts) after selecting timer operating mode and setting the tai register. ? the tai register indicates a counter value while coun ting at any given time. however, ffffh can be read if the timer underflows or 0000h if the timer overflow s, in the reload timing. a setting value can be read between setting the tai register while a counter stops and starting a counter. m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 343 of 352 rej09b0385-0100 24.7.2.3 timer a (one-shot timer mode) ? the tais bit (i = 0 to 4) in the tabsr register is set to 0 (count stops) after reset. set the tais bit to 1 (count starts) after selecting timer operating mode and setting the tai register. ? the following occurs when the tais bit in the tabsr register is set to 0 (count stops) while counting. ? the counter stops counting and the contents of the reload register is reloaded. ? the taiout pin outputs a low-level (?l?) signal. ? the ir bit in the taiic register becomes 1 (i nterrupt requested) af ter one cpu clock cycle. ? one-shot timer is operated by an intern al count source. when an external trigger is selected, a maximum of one count source clock delay occurs be tween the trigger input to the taiin pin and the one-shot timer output. ? the ir bit becomes 1 when one of the following pr ocedures are used to set timer operating mode. ? when selecting one-shot timer mode after reset. ? when switching from timer mode to one-shot timer mode. ? when switching from event counter mode to one-shot timer mode. to use the timer ai interrupt (ir bit), set the ir bit to 0 after one of the above setting has done. ? when a retrigger occurs while counting, the contents of the reload register is reloaded after the counter decrements by one, and continues counting. to generate a retrigger while counting, wait 1 count source clock cycle or more after the last trigger. ? when an external trigger input is selected to start counting in timer a one-shot timer mode, do not provide an external retrigger input for 300 ns before a timer a counter va lue reaches 0000h. one-shot timer may stop counting. (technical update: tn-16c-125a/ea) 24.7.2.4 timer a (pulse width modulation mode) ? the tais bit (i = 0 to 4) in the tabsr register is set to 0 (count stops) after reset. set the tais bit to 1 (count starts) after selecting timer operating mode and setting the tai register. ? the ir bit becomes 1 when one of the following pr ocedures are used to select timer operating mode. ? when selecting pwm mode after reset. ? when switching from timer mode to pwm mode. ? when switching from event counter mode to pwm mode. to use the timer ai interrupt (ir bit), set the ir bit to 0 after one of the above setting has done. ? the following occurs when the tais bit is set to 0 (count stops) while pwm pulse is output. ? the counter stops. ? if the taiout pin outputs a high-level (?h?) signal, the signal changes to ?l? and the ir bit becomes 1. ? if the taiout pin outputs an ?l? signal, its output signal and the ir bit remains unchanged. m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 344 of 352 rej09b0385-0100 24.7.3 timer b 24.7.3.1 timer b (timer m ode, event counter mode) ? the tbis bit (i = 0 to 5) in the tabsr or tbsr regist er is set to 0 (count stops) after reset. set the tbis bit to 1 (count starts) after selecting timer operating mode and setting the tbi register. bits tb2s to tb0s are bits 7 to 5 in the tabsr regist er. bits tb5s to tb3s are bits 7 to 5 in the tbsr register. ? the tbi register indicates a counter value while counting at any given time. however, ffffh can be read in the reload timing. a setting value can be read between setting the tbi register while a counter stops and starting a counter. 24.7.3.2 timer b (pulse period/pulse width measurement mode) ? to set the mr3 bit to 0 (no overflow), wait for one or more count source cycles to write to the tbimr register after the mr3 b it becomes 1, while the tbis bit is set to 1. (technical update: tn-m16c-75-0110) ? use the ir bit in the tbiic register to detect overflow. the mr3 bit is used only to determine an interrupt request source within the interrupt routine. ? when the first valid edge is input after the count st arts, an undefined value is transferred to the reload register. at this time, the timer bi interrupt request is not generated. ? the counter value is undefined when the count starts. therefore, the mr3 bit may become 1 (overflow) and causes a timer bi interrupt request to be generated before a valid edge is input. ? the ir bit may become 1 (interrupt requested) by chan ging bits mr1 and mr0 in the tbimr register after the count starts. if the same value is written to bits mr1 and mr0, the ir bit is not changed. ? pulse width is repeatedly measured in pulse width measurement mode. determine by program whether the measurement result is high (?h?) or low (?l?). ? if an overflow and a valid edge input occur simultaneously in pulse period measurement mode, an interrupt request is generated only once, which results in the va lid edge not being recognized. do not let an overflow occur. ? in pulse width measurement mode, determine whether an interrupt source is a valid edge input or an overflow by reading the port level in the tbi interrupt routine. m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 345 of 352 rej09b0385-0100 24.8 three-phase motor control timer function ? do not write to the tai or the tai1 register (i = 1, 2, 4) in the timing that timer b2 underflows. if there is a possibility to write in this timing, read the value of the ti mer b2 register to verify that there is a sufficient time until timer b2 underflows, and then write to the tai or the tai1 register immediately. (technical update: tn-m16c-86-0205) m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 346 of 352 rej09b0385-0100 24.9 serial interfaces 24.9.1 changing uibrg re gister (i = 0 to 4) set the uibrg register after setting bits clk1 and clk0 in the uic0 register. when bits clk1 and clk0 are changed, the uibrg regist er must be set again. 24.9.2 clock synchronous mode 24.9.2.1 transmit operation if an external clock is selected, the following conditions must be met while the external clock is held ?h? when the ckpol bit in the uic0 register (i = 0 to 4) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the se rial clock), or while the external clock is held ?l? when the ckpol bit is set to 1 (transmit data output at the rising edge and recei ve data input at the fallin g edge of the serial clock) ? set the te bit in the uic1 register to 1 (transmit operation enabled). ? set the re bit in the uic1 register to 1 (receive operation enabled). ? the ti bit in the uic1 register is 0 (data in the uitb register). the re bit setting is not required for a transmit-only operation. 24.9.2.2 receive operation ? in clock synchronous mode, the serial clock is controlled by the transmit control circuit. set the uarti- associated registers for a transmit operation as well, even if the mcu is used only for receive operation. dummy data is output from the txdi pin while r eceiving if the txdi pin is set to output mode. ? if data is received continuously, an ove rrun error occurs when the ri bit in the uic1 register is 1 (data in the uirb register) and the seventh bit of the next data is received in the uarti receive shift register. and the oer bit in the uirb register becomes 1 (overrun error o ccurred). in this case, the uirb register becomes undefined. if an overrun error occurs, the ir bi t in the siric register is not changed to 1. ? the following two conditions must be satisfied to use continuous receive mode (uirrm bit is set to 1). (1) the ckdir bit in the uimr register is set to 1 (external clock). (2) the rts function is not used. to receive data continuous ly under the other conditions, set the uirrm bit to 0 (continuous receive mode disabled), and write dumm y data to the uitb register every ti me a receive operation is completed. 24.9.3 uart mode set the uiere bit in the uic1 register after setting the uimr register. 24.9.4 special mode 1 (i 2 c mode) to generate the start condition, stop condition, or rest art condition, set the stspsel bit in the uismr4 register to 0. then, wait for a half clock cycle of the serial clock or more to change individual condition generation bit (the stareq bit, stpreq bit, or rstareq bit) from 0 to 1. (technical update: tn-16c-130a/ea) m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 347 of 352 rej09b0385-0100 24.10 a/d converter ? set the adst bit to 1 (a/d conversion starts) af ter setting registers ad0con0 (adst bit excluded), ad0con1, ad0con2, ad0con3, and ad0con4. ? when the vcut bit in the ad0con1 register is changed from 0 (vref not connected) to 1 (vref connected), wait for 1 s or more to start a/d conversion. set the vcut bit to 0 when a/d conversion is not used to reduce power consumption. ? to prevent latch-up and malfunction due to noise and al so to minimize a conversion error, insert a capacitor between the avss pin and each of th e following pins: the av cc pin, vref pin, or analog input pin ani_j (i = none, 15; j = 0 to 7). insert a capacitor between the vcc pin and the vss pin as well. figure 24.4 shows an example of individual pin handling. figure 24.4 individual pin handling ? set the port direction bit in the pdk register (k = 0 to 15 ), which corresponds to a pin used as an analog input pin, to 0 (input mode). also, set the port directio n bit in the pdk register corresponding to the adtrg pin, to 0 (input mode.) ? when the key input interrupt is used, do not select pins p10_4 to p10_7 (an_4 to an_7) as analog input pins. ? ad frequency must be 16 mhz or lower when vcc1 = 4.2 v to 5.5 v, or 10 mhz or lower when vcc1 = 3.0 v to 5.5 v. when the sample and hold is not activated, ad frequency must be 250 khz or higher. when the sample and hold is activated, ad frequency must be 1 mhz or higher. ? when a/d operating mode is changed, set bits ch2 to ch0 in the ad0con0 register or bits scan1 and scan0 in the ad0con1 register agai n to select analog input pins. ? the voltage applied to an_0 to an_7, an15_0 to an15_7, anex0, and anex1 must be vcc1 or below. vcc1 vss avcc avss vref ani c4 c1 c2 c3 mcu notes: 1.c1 0.47 f, c2 0.47 f, c3 10000 pf, c4 0.1 f, c5 0.1 f (reference values) 2.use thick and shortest po ssible wiring to connect capacitors. vcc2 vss c5 vcc1 vcc2 vcc1 m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 348 of 352 rej09b0385-0100 ? if an a/d conversion in progress is forcibly aborte d by setting the adst bit in the ad0con0 register to 0 (a/d conversion stops), the a/d conversion result wi ll be incorrect. the ad0i register which is not performing a/d conversion may also be incorrect. if the adst bit is set to 0 during a/d conversion, do not use values obtained from any of ad0i registers. ? external triggers cannot be used in dmac operating mode . do not read the ad00 register using instructions. ? do not perform a/d conversion in wait mode. ? to abort an a/d conversion in progress by setting the ad st bit in the ad0con0 register to 0 in single sweep mode, disable interrupts before setting the adst bit to 0. (technical update: tn-16c-132a/ea) m32c/8a group 24. usage notes rev.1.00 jul 15, 2007 page 349 of 352 rej09b0385-0100 24.11 programmable i/o ports ? pins p7_2 to p7_5, p8_0, and p8_1 have the forced cutoff function of the three-phase pwm output. when these ports are set in output mode (port output, timer output, three-phase pwm output, serial interface output), they are affected by the three-phase motor control timer function and the nmi pin setting. table 24.5 shows the invc0 register setting, nmi pin input level, and output pin states. table 24.5 invc0 register setting, nmi pin level, and output pin status ?: not affected by the bit setting nor the pin state note: 1. the inv03 bit becomes 0 after a low-level (?l?) signal is applied to the nmi pin. ? the availability of the pull-up resistors is undefined un til the internal power voltage stabilizes even if the reset pin is held ?l?. setting value of the invc0 register nmi pin input level pin states of p7_2 to p7_5, p8_0, p8_1 (when set in output mode) inv02 bit inv03 bit 0 (three-phase motor control timer function not used) ?? output functions selected using registers ps1, psl1, psc, ps2, and psl2 1 (three-phase motor control timer function used) 0 (three-phase motor control timer output disabled) ? high-impedance states 1 (three-phase motor control timer output enabled) (1) h output functions selected using registers ps1, psl1, psc, ps2, and psl2 l (forcibly terminated) high-impedance states m32c/8a group appendix 1. package dimensions rev.1.00 jul 15, 2007 page 350 of 352 rej09b0385-0100 appendix 1. package dimensions terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0.27 0.22 0.17 max nom min dimension in millimeters symbol reference 20.1 20.0 19.9 d 20.1 20.0 19.9 e 1.4 a 2 22.2 22.0 21.8 22.2 22.0 21.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 * 1 * 2 * 3 x index mark y h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. e terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e m32c/8a group index rev.1.00 jul 15, 2007 page 351 of 352 rej09b0385-0100 [ a ] ad00 to ad07 ................................................... 258 ad0con0 ........................................................... 254 ad0con1 ........................................................... 255 ad0con2 ........................................................... 256 ad0con3 ........................................................... 257 ad0con4 ........................................................... 258 aier ..................................................................... 115 [ c ] cm0 ............................................................... 71 , 118 cm1 ........................................................................ 72 cm2 ........................................................................ 74 cpsrf ................................................................... 77 crcd ................................................................... 274 crcin .................................................................. 274 [ d ] d4int ..................................................................... 39 da0 ....................................................................... 273 da1 ....................................................................... 273 dacon ................................................................ 273 dct0 to dct3 .................................................. 125 dm0sl to dm3sl ............................................ 122 dma0 to dma3 ................................................. 124 dmd0 ................................................................... 126 dmd1 ................................................................... 127 dra0 to dra3 .................................................. 125 drc0 to drc3 ................................................. 125 ds ............................................................................ 49 dsa0 to dsa3 .................................................. 124 dtt ....................................................................... 186 [ e ] ewcr0 to ewcr3 ........................................... 55 [ i ] ictb2 ................................................................... 185 idb0 ...................................................................... 187 idb1 ...................................................................... 187 ifsr ............................................................ 113 , 205 interrupt control register (1) ....................... 103 interrupt control register (2) ....................... 104 invc0 ................................................................... 180 invc1 ................................................................... 181 [ m ] mcd ........................................................................ 73 mod ...................................................................... 136 [ o ] onsf .................................................................... 153 [ p ] p0 to p15 ............................................................ 285 pcr ....................................................................... 295 pd0 to pd15 ...................................................... 284 plc0 ....................................................................... 75 plc1 ....................................................................... 75 pm0 ......................................................................... 46 pm1 ......................................................................... 47 pm2 ......................................................................... 76 prcr ..................................................................... 94 ps0 ........................................................................ 286 ps1 ........................................................................ 286 ps2 ........................................................................ 287 ps3 ........................................................................ 287 psc ....................................................................... 290 psl0 ..................................................................... 288 psl1 ..................................................................... 288 psl2 ..................................................................... 289 psl3 ..................................................................... 289 pur0 .................................................................... 291 pur1 .................................................................... 291 pur2 .................................................................... 292 pur3 .................................................................... 293 pur4 .................................................................... 294 pwcr0 .................................................................. 66 pwcr1 .................................................................. 67 [ r ] rlvl ........................................................... 105 , 134 rmad0 to rmad7 .......................................... 115 [ t ] ta0 to ta4 .......................................................... 149 ta0mr to ta4mr ............... 145 , 146 , 147 , 148 ta1, ta2, ta4, ta11, ta21, ta41 ............. 187 ta1mr, ta2mr, ta4mr .............................. 183 tabsr .............................................. 152 , 171 , 188 tb0 to tb5 ......................................................... 170 index m32c/8a group index rev.1.00 jul 15, 2007 page 352 of 352 rej09b0385-0100 tb0mr to tb5mr ........................ 167 , 168 , 169 tb2 ........................................................................ 186 tb2mr ................................................................. 182 tb2sc ................................................................. 185 tbsr .................................................................... 171 tcspr .......................................................... 77 , 144 trgsr ...................................................... 151 , 184 [ u ] u0brg to u4brg ........................................... 204 u0c0 to u4c0 ................................................... 203 u0c1 to u4c1 ................................................... 204 u0mr to u4mr ................................................ 198 u0rb to u4rb .................................................. 206 u0smr to u4smr .......................................... 199 u0smr2 to u4smr2 ..................................... 200 u0smr3 to u4smr3 ..................................... 201 u0smr4 to u4smr4 ..................................... 202 u0tb to u4tb ................................................... 206 udf ....................................................................... 150 [ v ] vcr1 ...................................................................... 38 vcr2 ...................................................................... 38 [ w ] wdc .............................................................. 40 , 119 wdts ................................................................... 119 [ x ] x0r to x15r ...................................................... 276 xyc ....................................................................... 276 [ y ] y0r to y15r ...................................................... 276 c - 1 revision history m32c/8a group hardware manual rev. date description page summary rev.1.00 jul 15, 2007 ? first edition issued m32c/8a group hardware manual publication data : rev.1.00 jul 15, 2007 published by : sales strategic planning div. renesas technology corp. ? 2007. renesas technology corp., all rights reserved. printed in japan 2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan m32c/8a group hardware manual |
Price & Availability of M308A0SGP
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |